MT48H8M32LFB5-75 IT:H Micron Technology Inc, MT48H8M32LFB5-75 IT:H Datasheet - Page 14

DRAM Chip Mobile SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray

MT48H8M32LFB5-75 IT:H

Manufacturer Part Number
MT48H8M32LFB5-75 IT:H
Description
DRAM Chip Mobile SDRAM 256M-Bit 8Mx32 1.8V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr

Specifications of MT48H8M32LFB5-75 IT:H

Density
256 Mb
Maximum Clock Rate
133 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
1.8 V
Maximum Random Access Time
8|6 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
256M (8Mx32)
Speed
133MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Package / Case
90-VFBGA
Organization
8Mx32
Address Bus
14b
Access Time (max)
8/6ns
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
100mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 6:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
Mode Register Definition
M14 M13
0
0
1
1
0
1
0
1
M8
0
Mode Register Definintion
Base mode register
Reserved
Extended mode register
Reserved
M9
M14
14
0
BA1
0
1
M7
0
M12, M11, M10 = “0, 0, 0”
M13
BA0 A12
13
0
to ensure compatibility
Programmed burst length
with future devices.
Single location access
M[6:0]
Valid
M12
Write Burst Mode
12
Reserved
Program
M11
11
A11
Normal operation
All other states reserved
Operating Mode
10
M10
A10
14
WB
M9
A9
9
OP Mode
M8
A8
8
M6
0
0
0
0
1
1
1
1
M7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A7
M5
7
0
0
1
1
0
0
1
1
CAS Latency
M4
M6
A6
6
0
1
0
1
0
1
0
1
256Mb: x16, x32 Mobile SDRAM
M5
5
A5
CAS Latency
M4
4
A4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BT
M3
2
3
A3
3
Burst Length
M2
0
0
0
0
1
1
1
1
M2
A2
2
M3
0
1
M1
0
0
1
1
0
0
1
1
M1
1
A1
©2006 Micron Technology, Inc. All rights reserved.
M0
Register Definition
0
1
0
1
0
1
0
1
M0
A0
0
Continuous
Reserved
Reserved
Reserved
M3 = 0
Interleaved
Burst Type
Sequential
Burst Length
1
2
4
8
Address Bus
Mode
Register (Mx)
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8

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