TMC2192KHC Fairchild Semiconductor, TMC2192KHC Datasheet - Page 24

• Manufacturer Part Number: TMC2192KHC
• Description: Video ICs
• Manufacturer: Fairchild Semiconductor
• Type: Encoderr

Specifications of TMC2192KHC

• Operating Supply Voltage: - 0.5 V to + 7 V
• Supply Current: 375 mA
• Maximum Operating Temperature: 70 C
• Package / Case: MQFP-100
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TMC2192
Enabling the pedestal on line 25 enables it for the remainder
of field 1, to line 262. Likewise, enabling the pedestal on line
288 enables it for the remainder of field 2.
Pedestal Height
PEDHGT1 determines the height of the pedestal for the
luminance channel on the composite path. The range of the
pedestal height is from -22.1 to 21.74 IRE in .345 IRE incre-
ments.
Sync and Blank Insertion
The composite paths blank and sync D/A codes are deter-
mined by the FORMAT control register. For NTSC and
PAL-M formats the blank D/A code is 240 (295 mV) and the
sync D/A code is 8 (9 mV). For all other PAL formats the
blank D/A code is 256 (314 mV) and the sync D/A code is
12 (14 mV).
In all cases the sync edges are sloped to insure the proper rise
and fall times in all video standards.
Closed Caption Insertion
Control Registers for this section
The TMC2192 includes a flexible closed-caption processor.
It may be programmed to insert a closed caption signal on
any line within a range of 16 lines on ODD and/or EVEN
fields. Closed Caption insertion overrides all other configura-
tions of the encoder: if it is specified on an active video line,
it takes precedence over the video data and removes NTSC
setup if setup has been programmed for the active video
lines. Closed Caption is only available when the TMC2192
is in a 13.5 MHz pixel rate.
Closed caption is turned on by setting CCON HIGH. When-
ever the encoder begins producing a line specified by
CCFLD and CCLINE, it will insert a closed caption line in
its place. If CCRTS is HIGH, the data contained in CCDx
will be sent. IF CCRTS is LOW, Null bytes (hex 00 with
ODD parity) will be sent.
24
Address
0x1C
0x1D
0x1E
0x1E
0x1E
0x1E
0x1E
Bit(s)
7-6
1-0
7
6
5
4
3–0
Name
CCD1
CCD2
CCON
CCRTS
CCPAR
CCFLD
CCLINE
Line Selection
The line to contain CC data is selected by a combination of
the CCFLD bit and the CCLINE bits. CCLINE is added to
the offset shown in Table 16 to specify the line.
Table 13. Closed Caption Line Selection
Parity Generation
Standard Closed-Caption signals employ ODD parity, which
may be automatically generated by setting CCPAR HIGH.
Alternatively, parity may be generated externally as part of
the bytes to be transmitted, and, with CCPAR LOW, the
entire 16 bits loaded into the CCDx registers will be sent
unchanged.
Operating Sequence
A typical operational sequence for closed-caption insertion
on line xx is:
As soon as CCDx s transferred into the CC processor (and
CCRTS goes LOW), new data may be loaded into registers
1C and 1D. This allows the user to transmit CC data on sev-
eral consecutive lines by loading data for line n+1 while data
is being sent on line n.
Standard
525
625
Read Register 1E and check that bit 7 is LOW, indicat-
ing that the CCDx registers are ready to accept data.
If ready, write two bytes of CC data into registers 1C
and 1D.
Write into register 1E the proper combination of
CCFLD and CCLINE. CCPAR may be written as
desired. Set CCRTS HIGH.
The CC data is transmitted during the specified line.
Offset
12
274
16
328
Field
ODD
EVEN
ODD
EVEN
PRODUCT SPECIFICATION
REV. 1.0.0 8/13/03
Lines
12-27
274-289
16-31
328-343