HUFA75429D3ST Fairchild Semiconductor, HUFA75429D3ST Datasheet - Page 7

• Manufacturer Part Number: HUFA75429D3ST
• Description: MOSFET N-CH 60V 20A DPAK
• Manufacturer: Fairchild Semiconductor
• Series: UltraFET™r

Specifications of HUFA75429D3ST

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 25 mOhm @ 20A, 10V
• Drain To Source Voltage (vdss): 60V
• Current - Continuous Drain (id) @ 25° C: 20A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 85nC @ 20V
• Input Capacitance (ciss) @ Vds: 1090pF @ 25V
• Power - Max: 125W
• Mounting Type: Surface Mount
• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.021 Ohms
• Drain-source Breakdown Voltage: 60 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 20 A
• Power Dissipation: 125 W
• Maximum Operating Temperature: + 175 C
• Mounting Style: SMD/SMT
• Fall Time: 33 ns
• Minimum Operating Temperature: - 55 C
• Rise Time: 39 ns
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2003 Fairchild Semiconductor Corporation
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
mal resistance of the heat dissipating path determines the
maximum allowable device power dissipation, P
application. Therefore the application’s ambient tempera-
ture, T
reviewed to ensure that T
mathematically represents the relationship and serves as
the basis for establishing the rating of the part.
In using surface mount devices such as the TO-252 pack-
age, the environment in which it is applied will have a signif-
icant influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
2. The number of copper layers and the thickness of the
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
Fairchild provides thermal information to assist the design-
er’s preliminary application evaluation. Figure 20 defines the
R
nent side) area. This is for a horizontally positioned FR-4
board with 1oz copper after 1000 seconds of steady state
power with no air flow. This graph provides the necessary in-
formation for calculation of the steady state junction temper-
ature or power dissipation. Pulse applications can be
evaluated using the Fairchild device Spice thermal model or
manually utilizing the normalized maximum transient ther-
mal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 20 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
R
P
whether there is copper on one side or both sides of the
board.
board.
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
JA
DM
JA
for the device as a function of the top copper (compo-
A
=
(
=
o
-----------------------------
C), and thermal resistance R
T
33.32
JM
R
–
JA
T
+
A
------------------------------------ -
0.268
23.84
JM
+
is never exceeded. Equation 1
Area
JA
JM
(
o
C/W) must be
DM
, and the ther-
is complex
DM
(EQ. 1)
(EQ. 2)
, in an
Figure 20. Thermal Resistance vs Mounting
125
100
75
50
25
0.01
AREA, TOP COPPER AREA (in
0.1
Pad Area
R
JA
= 33.32 + 23.84/(0.268+Area)
1
2
)
10
Rev. A1