COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 39

• Manufacturer Part Number: COM20022I3V-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20022I3V-HD

• Data Rate: 10 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
SMSC COM20022I 3V
BIT
BIT
5-4
2-0
7-0
7
6
3
Read Data
Auto Increment
(Reserved)
DMA Enable
Address 10-8
Address 7-0
BIT NAME
BIT NAME
RDDATA
AUTOINC
DMAEN
A10-A8
A7-A0
SWAP
Table 6.8 - Address Pointer High Register
Table 6.9 - Address Pointer Low Register
SYMBOL
SYMBOL
DATASHEET
This bit tells the COM20022I 3V whether the following
access will be a read or write. A logic "1" prepares the
device for a read, a logic "0" prepares it for a write.
This bit controls whether the address pointer will
increment automatically. A logic "1" on this bit allows
automatic increment of the pointer after each access,
while a logic "0" disables this function. Please refer to the
Sequential Access Memory section for further detail.
These bits are undefined.
This bit is used to Disable/Enable the assertion of the
DMA Request (DREQ pin) after writing the Address
Pointer Low register. DMAEN=0: Disable (Default).
DMAEN=1: Enable the assertion of the DREQ pin after
writing the Address Pointer Low register. Writing
DMAEN=0 during the DMA operation will negate the
DREQ pin immediately. The DMA operation is terminated
immediately after the next DACK pin negation. The
inverting signal of DAMEN is the Interrupt source signal
DMAEND. The DMAEN bit is cleared automatically by
finishing the DMA. If the DMAEND bit in the Mask register
is not masked, the Interrupt occurs by finishing the DMA
operation.
These bits hold the upper three address bits which
provide addresses to RAM.
These bits hold the lower 8 address bits which provide the
addresses to RAM.
When 16 bit access is enabled, (W16=1), A0 becomes the
SWAP bit. Swap bit is undefined after a hardware reset.
The swap bit must be set before W16 bit is set to “1”. The
swap bit is used to swap the upper and lower data byte.
The swap bit influences both CPU cycle and DMA cycle.
See Table Below.
Detected Host
Interface Mode
Intel 80xx Mode
(RD, WR Mode)
Motorola 68xx Mode
(DIR, DS Mode)
Page 39
DESCRIPTION
DESCRIPTION
Swap Bit
0
1
0
1
D15-D8
Even
Even
Odd
Odd
Pin
D7-D0
Even
Even
Odd
Odd
Revision 02-27-06
Pin