COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 22
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COM20022I3V-HD
Manufacturer Part Number
COM20022I3V-HD
Description
Network Controller & Processor ICs ARCNET Contrllr
Manufacturer
SMSC
Datasheet
1.COM20022I3V-HD.pdf
(83 pages)
Specifications of COM20022I3V-HD
Data Rate
10 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
TQFP-48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Revision 02-27-06
(Active-High)
(Active-Low)
nDACK
The timing of the Non-Burst mode DMA data transfer is found in the Timing Diagrams section of this data
sheet. The basic sequence of operation is as follows:
DREQ
nDACK becomes active (low) upon DREQ becoming active (high) and catching the host bus (AEN=1).
DREQ becomes inactive after nDACK and read/write signal become active.
DREQ becomes active after nDACK or read/write signal becomes inactive.
DREQ becomes inactive after TC and the read/write signal assert (when nDACK=0). In this case,
DREQ doesn't become active again after nDACK becomes inactive.
nDACK becomes inactive after DREQ=0 and the present cycle finishes.
Figure 5.4
- Programmable Burst Mode DMA Transfer (Rough Timing)
(Counting Read/Write pulse
or counting internal timer)
DATASHEET
Transfer term
Page 22
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Gate
Time
SMSC COM20022I 3V
Transfer
Restart
Datasheet
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