COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet

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... Automatically Detects Type of Microcontroller Interface 2Kx8 On-Chip Dual Port RAM Command Chaining for Packet Queuing Sequential Access to Internal RAM Software Programmable Node ID COM20022I3V-HD for 48 Pin TQFP Package COM20022I3V-HT for 48 Pin TQFP Package (Green, Lead-free) SMSC COM20022I 3V COM20022I 3V 10 Mbps ARCNET (ANSI 878.1) Controller with ...

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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“ ...

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... Diagnostic Status Register .....................................................................................................................33 6.2.8 Command Register.................................................................................................................................34 6.2.9 Address Pointer Registers ......................................................................................................................34 6.2.10 Configuration Register ........................................................................................................................34 6.2.11 Sub-Address Register .........................................................................................................................34 6.2.12 Setup 1 Register .................................................................................................................................34 6.2.13 Setup 2 Register .................................................................................................................................34 6.2.14 Bus Control Register ...........................................................................................................................35 6.2.15 DMA Count Register ...........................................................................................................................36 6.3 Internal RAM ..................................................................................................................................... 46 SMSC COM20022I 3V TABLE OF CONTENTS Page 3 DATASHEET Revision 02-27-06 ...

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... Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................65 Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................66 Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................67 Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM LIST OF FIGURES Page 4 DATASHEET Datasheet SMSC COM20022I 3V ...

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... Table 6.10 - Sub Address Register ...............................................................................................................................40 Table 6.11 - Configuration Register ..............................................................................................................................40 Table 6.12 - Setup 1 Register .......................................................................................................................................42 Table 6.13 - Setup 2 Register .......................................................................................................................................43 Table 6.14 - Bus Control Register.................................................................................................................................44 Table 6.15 - DMA Count Register.................................................................................................................................45 Table 8.1 - DMA Timing................................................................................................................................................77 Table 8 Pin TQFP Package Parameters ............................................................................................................79 SMSC COM20022I 3V LIST OF TABLES Page 5 DATASHEET Revision 02-27-06 ...

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... Chapter 1 General Description SMSC's COM20022I member of the family of Embedded ARCNET Controllers from Standard Microsystems Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in industrial, automotive, and embedded control environments using an ARCNET protocol engine. interfaces, eight- page message support, and extended temperature range of the COM20022I 3V make it the only true network controller optimized for use in industrial, embedded, and automotive applications ...

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... D10 AD2 4 D11 5 6 VSS VDD VSS Ordering Information: COM20022 SMSC COM20022I COM20022I 3V COM20022 48 Pin TQFP 48 Pin TQFP PACKAGE TYPE: TQFP TEMP RANGE: (Blank) = Commercial: 0°C to +70° Industrial: -40°C to +85°C DEVICE TYPE: 20022 = Universal Local Area Network Controller ...

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... L: High speed timing mode (only for non-multiplexed bus) H: Normal timing mode This signal is connected to internal pull-up registers. OUT DMA Request signal. Active polarity is programmable. Default is active high. IN DMA Acknowledge signal. Active Low. When BUSTMG is High, this signal is connected to internal pull-up registers Page 8 DATASHEET Datasheet SMSC COM20022I 3V ...

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... Supply 32,43 6,11, Ground VSS 18,23, 30,41 19,27 N/C N/C SMSC COM20022I 3V I/O DESCRIPTION IN Terminal Count signal. Active polarity is programmable. Default is active high. When BUSTMG is High, this signal is connected to the internal pull-up resistor. IN Refresh execution signal. Falling edge detection. This signal is connected to the internal pull-up resistor ...

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... CRC No OK? Increment Y N Activity NID for 18.7 us? LENGTH OK? DID =0? N DID =ID? Y SEND ACK - COM20022I 3V Operation Figure 3.1 Page 10 DATASHEET Datasheet Activity for 20.5 uS Set NID= Broadcast Enabled? Start Timer: Y T=(255-ID 36.5 us Activity Y On Line T= Set RI N SMSC COM20022I 3V ...

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... FM radio band not practical for use for noise emission reasons. Therefore, higher frequency clocks are generated from the 20 MHz crystal as selected through two bits in the Setup2 register, CKUP[1,0] as shown below. The selected clock is supplied to the ARCNET controller. SMSC COM20022I 3V CLOCK DATA RATE Div ...

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... ID number on the network, but is typically within the range 15.3 mS. Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM CLOCK FREQUENCY (DATA RATE MHz (Up to 2.5Mbps) Default (Bypass MHz (Up to 5Mbps) 0 Reserved 1 80 MHz (Only 10Mbps) Page 12 DATASHEET Datasheet During NETWORK SMSC COM20022I 3V ...

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... Unlike asynchronous protocols, there is a constant amount of time separating each data byte Mbps network, each byte takes exactly 11 clock intervals of 100ns each result, one byte is transmitted every 1.1 SMSC COM20022I 3V S and the time to transmit a message can be Page 13 ...

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... Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X ALERT SOH BURST Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM EOT DID ENQ DID SID DID DID COUNT data Page 14 DATASHEET Datasheet DID DID data CRC CRC SMSC COM20022I 3V ...

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... An ACK (ACKnowledgement--ASCII code 86H) character 4.6.5 Negative Acknowledgements A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character SMSC COM20022I 3V ALERT BURST ACK ALERT BURST NAK Page 15 DATASHEET ...

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... Whenever the pointer is loaded for reads with a new value, data is immediately prefetched to prepare for the first read operation. Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 16 DATASHEET Datasheet Once the type of bus is SMSC COM20022I 3V ...

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... RESET nRD nWR nINT1 8051 RXIN TXEN nPULSE1 nPULSE2 GND BACKPLANE CONFIGURATION FIGURE A - Multiplexed, 8051 - Like Bus Interface with RS-485 Interface Figure 5.1 SMSC COM20022I 3V COM20022 AD0-AD2, D3-D7 A2/BALE RXIN nCS nRESET nTXEN nPULSE1 nRD/nDS nPULSE2 nWR/DIR GND nINTR Differential Driver ...

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... GND 4, 13 Traditional Hybrid 0. *Valid for 2.5 Mbps only. uF FIGURE C Page 18 DATASHEET Datasheet RXIN 75176B or Equiv. TXEN GND Differential Driver Configuration * Media Interface may be replaced with Figure 0.47 uF 0.01 uF 1KV Configuration SMSC COM20022I 3V ...

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... Bus Control Register: DRPOL, TCPOL and DMAMD[1,0]. The DRQPOL bit sets the active polarity of the DREQ pin; the TCPOL bit sets the active polarity of the TC pin; the DMAMD[1,0] bits select the data transfer mode of the DMA. SMSC COM20022I 3V SWAP BIT (NOTE) D15-D8 PINS ...

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... The DREQ pin stays asserted until the TC pin goes High. In Programmable-Burst mode, the gating can be by timer or by cycle counter. Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 20 DATASHEET Datasheet time after writing the ARB time after writing the ARB SMSC COM20022I 3V ...

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... DMA cycles is approximately 1uS. The DMA overhead time is approximately 2.5μS. The Refresh execution time is 500nS. This computes to 15μS - 2.5μS - 500nS = 12μ cycles. Therefore the DREQ pin must be negated every 12 cycles. Figure 5.4 illustrates the rough timing of the Programmable- Burst mode DMA transfer. SMSC COM20022I 3V minimum 4T ARB Writing Address ...

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... DREQ doesn't become active again after nDACK becomes inactive. nDACK becomes inactive after DREQ=0 and the present cycle finishes. Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Transfer term (Counting Read/Write pulse or counting internal timer) Page 22 DATASHEET Datasheet Gate Time Restart Transfer SMSC COM20022I 3V ...

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... RAM functions as a memory to I/O DMA transfer. Since it is treated as an I/O device, the COM20022I 3V has to create the RAM address. Therefore the COM20022I 3V’s address pointers must be programmed before starting the DMA transfers. SMSC COM20022I 3V Page 23 DATASHEET ...

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... Chip Select (nCS) are sampled internally by Flip-Flops on the falling edge of the internal delayed nRD signal. The internal real read signal is the more delayed nRD signal. But the rising edge of Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 24 DATASHEET Datasheet SMSC COM20022I 3V ...

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... The RBUSTMG bit was added to Disable/Enable the High Speed CPU Read function defined as: RBUSTMG=0, Disabled (Default); RBUSTMG=1, Enabled. In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply. BUSTMG PIN RBUSTMG BIT SMSC COM20022I 3V VALID VALID BUS TIMING MODE X High Speed CPU Read and Write 0 Normal Speed CPU Read and Write ...

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... Hybrid offers isolation for the safety of the system and offers high Common Mode Rejection. The Traditional Hybrid Interface uses circuits like SMSC's HYC9068 or HYC9088 to transfer the pulse-encoded data between the cable and the COM20022I 3V. The COM20022I 3V transmits a logic "1" by generating two 100nS non-overlapping negative pulses, nPULSE1 and nPULSE2. Lack of pulses indicates a logic " ...

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... RXIN is connected to nPULSE1 to make the serial backplane data line. A ground line (from the coax or twisted pair) should run in parallel with the signal. For applications requiring different treatment of the receive signal (like filtering or squelching), nPULSE1 and RXIN remain as independent pins. SMSC COM20022I 3V +VCC +VCC ...

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... Backplane Mode operation. The nPULSE2 pin should remain grounded at all times if an active high polarity is desired. Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 28 DATASHEET Datasheet coupled SMSC COM20022I 3V ...

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... IBM Type 1 (Note 5.1) Belden #89688 IBM Type 3 (Note 5.1) Telephone Twisted Pair Belden #1155A COMCODE 26 AWG Twisted Pair Part #105-064-703 Note 5.1 Non-plenum-rated cables of this type are also available. SMSC COM20022I RAM STATUS/ COMMAND REGISTER MICRO- SEQUENCER AND WORKING REGISTERS ...

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... TMA TA/ TTA NEW TENTID X NEXTID A10 A0/ SWAP SUB-AD2 SUB-AD1 SUB-AD0 BACK- SUB-AD1 SUB-AD0 PLANE TID2 TID1 TID0 NID2 NID1 NID0 CKP2 CKP1 SLOW- ARB NXT NXT ID1 NXT ID0 ID2 NO-SYNC RCN-TM1 RCM-TM2 SMSC COM20022I 3V ADDR 07-0 07-1 07-2 07-3 07-4 ...

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... FOUR NAKS 07 07-4 RBUS- 0 TMG 07-5 W16 0 07-6 TC7/ TC6/ TIM7/ TIM6/ CYC7 CYC6 SMSC COM20022I 3V READ ITCEN/ TC8/ DMA-MD1 RTRG RSYN/ GTTM TC5/ TC4/ TC3/ TIM5/ TIM4/ TIM3/ CYC5 CYC4 CYC3 Table 6.2 - Data Register at 16 Bit Access BIT1 BIT1 ...

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... When using the Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Table 6.4 - Data Register at 16 Bit Address BIT1 BIT1 BIT9 BIT8 BIT7 D11 D10 Page 32 DATASHEET BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 SMSC COM20022I 3V Datasheet BIT0 ADDR D0 04 ...

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... The COM20022I 3V Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20022I 3V, the COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration Register ...

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... Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register). This register contains bits for various functions. The CKUP1,0 bits select the clock to be generated from Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 34 DATASHEET Datasheet Any SMSC COM20022I 3V ...

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... RTRG = 1, the deasserted DREQ pin is reasserted by the timeout of the internal timer (350 ns or 750 ns, as selected by the GTTM bit.) See Figure 6.1 following. RTRG=0 nREFEX DREQ nDACK nWR/nRD Figure 6.1 - Illustration of the Effect of RTRG Bit on DMA Timing SMSC COM20022I 3V TIME-OUT PERIOD 0 210 26. ...

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... Transmit from Page fnn" command has been acknowledged. This bit should only be considered valid after the TA bit (bit 0) is set. Broadcast messages are never acknowledged. The TMA bit is cleared by issuing the "Enable Transmit from Page fnn" command. Page 36 DATASHEET Datasheet SMSC COM20022I 3V ...

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... New Next ID NEW NXTID 1,0 (Reserved) SMSC COM20022I 3V DESCRIPTION This bit, if high, indicates that the transmitter is available for transmitting. This bit is set when the last byte of scheduled packet has been transmitted out, or upon execution of a "Disable Transmitter" command. The TA bit is cleared by issuing the " ...

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... Please refer to the Command Chaining section for definition of this command. This command restarts the stopped internal operation after changing CKUP1 or CKUP0 bit. This command resets a mask bit of the DMAEND for clearing interrupt by DMA transfer finished. Page 38 DATASHEET Datasheet - SMSC COM20022I 3V ...

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... DMA Enable 2-0 Address 10-8 BIT BIT NAME 7-0 Address 7-0 SMSC COM20022I 3V Table 6.8 - Address Pointer High Register SYMBOL DESCRIPTION RDDATA This bit tells the COM20022I 3V whether the following access will be a read or write. A logic "1" prepares the device for a read, a logic "0" prepares it for a write. ...

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... CCHEN This bit, if high, enables the Command Chaining operation of the device. Please refer to the Command Chaining section for further details. A low level on this bit ensures software compatibility with previous SMSC ARCNET devices. TXEN When low, this bit disables transmissions by keeping nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN pin inactive ...

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... Extended Timeout 1,2 2 Backplane 1,0 Sub Address 1,0 SMSC COM20022I 3V SYMBOL DESCRIPTION ET1, ET2 These bits allow the network to operate over longer distances than the default maximum 1 mile by controlling the Response, Idle, and Reconfiguration Times. All nodes should be configured with the same timeout values for proper network operation ...

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... This bit, when set, will divide the arbitration clock by 2. Memory cycle times will increase when slow arbitration is selected. Note: For clock multiplier output clock speeds greater than 40 MHz, SLOWARB must be set. Defaults to low. Page 42 DATASHEET Datasheet DIVISOR SPEED 8 2.5Mbs 16 1.25Mbs 32 625Kbs 64 312.5Kbs 128 156.25Kbs SMSC COM20022I 3V ...

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... Clock Multiplier 3 Enhanced Functions 2 No Synchronous SMSC COM20022I 3V Table 6.13 - Setup 2 Register SYMBOL DESCRIPTION RBUSTMG This bit is used to Disable/Enable the High Speed CPU Read function for High Speed CPU bus support. RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable. That is, if BUSTMG (pin 26 and RBUSTMG = 1, High Speed CPU Read operations are enabled ...

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... RSYN = 0: DMA is started Immediately. RSYN = 1: DMA is started after Refresh execution. Programmable-Burst and Internal Re-Trigger mode: GTTM = 0: Gate Time is 350nS (min) GTTM = 1: Gate Time is 750nS (min) Page 44 DATASHEET Datasheet Time Out Period Max Node Count 210 255 nodes 52 nodes 26. nodes 13.125 mS nodes SMSC COM20022I 3V ...

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... DRQPOL BIT BIT NAME SYMBOL 7-0 Terminal Count TC7-TC0 Timer Mode TIM7-TIM0 Cycle Mode CYC7- CYC0 SMSC COM20022I 3V SYMBOL DESCRIPTION These bits select the data transfer mode of the DMA. These transfer modes influence the timing of asserting/negating the DREQ pin. DMAMD1 DMAMD0 ...

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... Auto Increment bit is set to logic "1", the device will automatically increment the address and place the Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Memory Data Bus 8 I/O Address 03H Low Memory Address Bus 11 Sequential Access Operation Page 46 DATASHEET Datasheet INTERNAL RAM SMSC COM20022I 3V The ...

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... The remaining portions of the buffer pages which are not allocated for current transmit or receive packets may be used as temporary storage for previous network data, packets to be sent later extra memory for the system, which may be indirectly accessed. SMSC COM20022I 3V Page 47 DATASHEET The ...

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... Command Chaining only requires two pages for transmit and two for receive (in this case, a total of four 256 byte pages, leaving 1K free). The general rule which may be applied to determine where in RAM a page begins is as follows: Address = (nn x 512 256). Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 48 DATASHEET Datasheet SMSC COM20022I 3V ...

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... If packets of these lengths must be sent, the user must add dummy bytes to the packet in order to make the packet fit into a long packet. SMSC COM20022I 3V LONG PACKET FORMAT ADDRESS ...

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... RAM buffer. Again, the appropriate buffer size is specified in the "Define Configuration" command. Typically, the page which just received the data packet will be read by the microcontroller at Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 50 DATASHEET Datasheet SMSC COM20022I 3V ...

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... Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are pipelined. In order for the COM20022I compatible with previous SMSC ARCNET device drivers, the device defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode must be enabled via a logic " ...

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... After reading the Status Register, the "Clear Receive Interrupt" command should be issued, thus resetting the TRI bit and clearing the interrupt. Note that only the "Clear Receive Interrupt" command will clear the Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 52 DATASHEET Datasheet Note that This SMSC COM20022I 3V ...

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... Writing to and reading from an odd address location from the COM20022I 3V's address space causes the COM20022I 3V to determine the appropriate bus interface. When the COM20022I 3V is powered on the SMSC COM20022I 3V The software reset does not affect the microcontroller This pulse width is used by the internal digital XTL ...

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... TXEN bit of the Configuration Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Reading the Diagnostic Status Register resets the MYRECON bit. Page 54 DATASHEET Datasheet SMSC COM20022I 3V ...

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... NODE ID already exists on the network. The software should periodically place values in the Tentative ID Register and monitor the New Next ID bit to maintain an updated network map. 6.6.3 Oscillator The COM20022I 3V contains circuitry which, in conjunction with an external parallel resonant crystal or TTL clock, forms an oscillator. SMSC COM20022I 3V Page 55 DATASHEET Revision 02-27-06 ...

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... The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390Ω pull-up resistor is required on XTAL1, while XTAL2 should be left unconnected. Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 56 DATASHEET Datasheet SMSC COM20022I 3V ...

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... RXIN) High Input Voltage 1 V IH1 (All inputs except A2, XTAL1, nRESET, nRD, nWR, nREFEX and RXIN) Low Input Voltage 2 V IL2 (XTAL1) High Input Voltage 2 V IH2 (XTAL1) SMSC COM20022I COM20022I 3V +85 A MIN TYP MAX 0.6 2.0 0.6 1.0 2.4 ...

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... SINK V I =-1mA SOURCE I =-200µA SOURCE (except DREQ, nIOCS16 =8mA SINK V I =-6mA SOURCE V I =12mA SINK V I =-5mA SOURCE V I =24mA SINK Open Drain Driver mA 5 Mbps mA 10 Mbps All Outputs Open μA V =0.0V IN μA V < V < SMSC COM20022I 3V ...

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... Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin. Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". SMSC COM20022I 3V = 1MHz 0V MIN TYP MAX 5.0 45 ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM VALID VALID DATA t1 t2 t12 t11 t6 t13 t5 t9 t16 t15 Invalid Valid Value Parameter if SLOW ARB = 0 opr if SLOW ARB = 1 from the trailing edge of nDS to ARB Page 60 DATASHEET Datasheet t7 t14 Note 2 t8 t10 min max units ARB SMSC COM20022I 3V ...

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... Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Notes 2 and 3 are applied to an access to Data Register by DMA transfer. Multiplexed Bus, 80XX-Like Control Signals; Read Cycle Figure 8.2 - SMSC COM20022I 3V VALID DATA VALID t1 t2, t4 ...

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... Invalid Valid Value MUST BE: BUSTMG pin = HIGH Parameter min Next )** 4T * ARB SLOW ARB = 0 opr from the trailing edge of nDS to the leading edge of the ARB from the trailing edge of nDS to ARB Page 62 DATASHEET Datasheet t7 Note 2 t8** t8 t14 t10 max units SMSC COM20022I 3V ...

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... Write cycle for Address Pointer Low Register occurring after a read from Data Note 3: Register requires a minimum of 5T leading edge of nWR. Notes 2 and 3 are applied to an access to Data Register by DMA transfer. - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle Figure 8.4 SMSC COM20022I 3V VALID VALID DATA t2 t10 ...

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... CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0 Parameter to nRD Low if SLOW ARB = 0 opr if SLOW ARB = 1 opr from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 64 DATASHEET Datasheet Note 2 t7 t12 min max units 5 ARB nS 40 40*** nS 0**** SMSC COM20022I 3V ...

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... Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Notes 2 and 3 are applied to an access to Data Register by DMA transfer. Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle Figure 8.6 - SMSC COM20022I 3V VALID Note 3 ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM VALID t10 t8 VALID DATA t12 VALID VALUE Parameter if SLOW ARB = 0 opr if SLOW ARB = 1 opr from the trailing edge of nDS to ARB Page 66 DATASHEET Datasheet t11 Note 2 t9 t13 min max units 5 ARB 40*** 0**** nS SMSC COM20022I 3V ...

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... Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle SMSC COM20022I 3V VALID ...

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... Next )** 4T * ARB 30*** 0***** if SLOW ARB = 0 opr from the trailing edge of nWR to the leading edge ARB from the trailing edge of nWR to the ARB from the trailing edge of nRD to the ARB Page 68 DATASHEET Datasheet Note 2 t5** t7 t12 max units 40**** nS nS SMSC COM20022I 3V ...

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... Write cycle for Address Pointer Low Register occurring after a read from Data Note 3: Register requires a minimum of 5T leading edge of nWR. Notes 2 and 3 are applied to an access to Data Register by DMA transfer. Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle SMSC COM20022I 3V VALID t10 ...

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... VALID DATA CASE 1: BUSTMG pin = HIGH min Next Time )** 4T * ARB 10 30*** 0***** if SLOW ARB = 0 opr from the trailing edge of nDS to the leading edge ARB from the trailing edge of nDS to ARB Page 70 DATASHEET Datasheet t13 t11 Note 2 t6 max units 40**** nS nS SMSC COM20022I 3V ...

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... Write cycle for Address Pointer Low Register occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Note 2 is applied to an access to Data Register by DMA transfer. Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle SMSC COM20022I 3V t12 VALID VALUE VALID t1 ...

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... Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Normal Mode Transmit or Receive Timing Page 72 DATASHEET Datasheet t5 LAST BIT (400 nS BIT TIME) t2 min typ max units 100 nS 400 nS 0 -10 +10 nS 950 nS 850 350 nS 250 nS 10 100 400 SMSC COM20022I 3V ...

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... DR *t2, t7, t10 = *t3, t11 = ** +/- **t13 = x T +/- Figure 8.14 (These signals are to and from the differential driver or the cable) SMSC COM20022I t10 t12 t11 Parameter - Backplane Mode Transmit or Receive Timing Page 73 DATASHEET t13 t8 LAST BIT (400 nS BIT TIME) min typ max units ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM t2 1.0V min + - - TTL Input Timing on XTAL1 Pin 400 nS) DR was over 4.5V. - Reset and Interrupt Timing Page 74 DATASHEET Datasheet t3 50 typ max units 100 10 20 MHz -200 200 ppm min typ max units * XTL **/ XTL SMSC COM20022I 3V ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Datasheet nCS t10 nREFEX t3 DREQ t2 nDACK TC nWR Write LOW-POINTER when DMAEN=1 nRD DATA (D15-D0) Note measured from the latest active timing among TC, Write/Read. Figure 8.17 SMSC COM20022I 3V t20 t19 t26 t21 t4 t1 t24 t25 t15 t11 t16 t12 t14 t9 ...

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... Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM t20 t19 t26 t21 t4 t1 t24 t25 t15 t16 VALID t11 t22 t23 t12 t14 t9 t8 VALID - DMA Timing (Motorola Mode 68XX) Page 76 DATASHEET Datasheet t19 t20 t7* t24 t25 VALID t22 t23 t13 t18 t17 VALID SMSC COM20022I 3V ...

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... DIR Setup to nDS Low (Motorola mode only) t23 DIR Hold from nDS High (Motorola mode only) t24 nDACK Setup to Write/Read Active t25 nDACK Hold After Write/Read Inactive t26 nREFEX Inactive Time SMSC COM20022I 3V Table 8.1 - DMA Timing MIN TYP 4 Tarb 5 Tarb 0 0 ...

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... Note 8.5 Conditions of CASE1W, CASE2W, CASE1R and CASE2R are shown below; CASE1W : BUSTMG pin = High CASE2W : BUSTMG pin = Low CASE1R : BUSTMG pin = High and RBUSTMG bit = 0 CASE2R : BUSTMG pin = Low or RBUSTMG bit = 1 Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 78 DATASHEET Datasheet SMSC COM20022I 3V ...

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... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4) Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is 0.78-1.08 mm. 5) Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC COM20022I 3V MAX ~ 1.6 0.10 ...

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... Data Rate is 10Mbps . This is done by changing the clock which is supplied to the Interrupt Disable logic. The frequency of this clock is always 20MHz even if the data rate is 10Mbps. Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Page 80 DATASHEET Datasheet SMSC COM20022I 3V ...

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... In this case, the interval time between the interrupt and writing Command is shorter than 3.2 μS. Setting the EF bit will cause the TA/RI bit to return to High upon release of the internal pulse signal for setting the TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 9.1 following. SMSC COM20022I 3V Page 81 DATASHEET ...

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... The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in the Configuration register. This solution is Enabled/Disabled by the EF bit. Revision 02-27-06 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM Tx/Rx completed prohibition period Tx/Rx completed Effect of the EF Bit on the TA/RI Bit Page 82 DATASHEET Datasheet SMSC COM20022I 3V ...

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... ISA Bus AEN SA15-SA4 12 SD15-SD0 16 nIOR nIOW SA2-SA0 3 IRQm 5V nIOCS16 DRQn nDACK TC nREFRESH RESETDRV Figure 10.1 - Example of Interface of Circuit Diagram to ISA Bus SMSC COM20022I 3V LS688x2 nG 12 bit Comparators P Q I/O Address Seeting (DIP Switches) P=Q 12 LS245x2 A 16 bit Bus Transceivers DIR ...