COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 30

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COM20022I3V-HD

Manufacturer Part Number
COM20022I3V-HD
Description
Network Controller & Processor ICs ARCNET Contrllr
Manufacturer
SMSC
Datasheet

Specifications of COM20022I3V-HD

Data Rate
10 Mbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
TQFP-48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
REGISTER
ADDRESS
ADDRESS
PTR HIGH
PTR LOW
SUB ADR
URATION
CONFIG-
NODE ID
STATUS
STATUS
NEXT ID
SETUP1
SETUP2
TENTID
DATA*
DIAG.
Chapter 6
6.1
Revision 02-27-06
RD-DATA
P1 MODE
NXT ID7
RECON
RESET
RBUS-
(R/W)*
RI/TRI
NID7
TMG
MSB
TID7
MY-
A7
D7
Microsequencer
The COM20022I 3V contains an internal microsequencer which performs all of the control operations
necessary to carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program
counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and
reconfiguration logic.
The COM20022I 3V derives a 20 MHz and a 10 MHz clock from the output clock of the Clock Multiplier.
These clocks provide the rate at which the instructions are executed within the COM20022I 3V. The 20
MHz clock is the rate at which the program counter operates, while the 10 MHz clock is the rate at which
the instructions are executed. The microprogram is stored in the ROM and the instructions are fetched
and then placed into the instruction registers. One register holds the opcode, while the other holds the
immediate data. Once the instruction is fetched, it is decoded by the internal instruction decoder, at which
point the COM20022I 3V proceeds to execute the instruction. When a no-op instruction is encountered,
the microsequencer enters a timed loop and the program counter is temporarily stopped until the loop is
complete. When a jump instruction is encountered, the program counter is loaded with the jump address
from the ROM.
microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of
the Diagnostic Status Register is set.
AUTO-INC
NXT ID6
CCHEN
DUPID
FOUR
NAKS
NID6
TID6
X/RI
D6
A6
X
0
Functional Description
The COM20022I 3V contains an internal reconfiguration timer which interrupts the
RCV-ACT
NXT ID5
CKUP1
TXEN
X/TA
TID5
NID5
A5
D5
X
0
X
Table 6.1 - Read Register Summary
DATASHEET
RCV- ALL
NXT ID4
TOKEN
CKUP0
NID4
POR
TID4
ET1
A4
D4
X
0
Page 30
READ
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
EXC-NAK
DMA-EN
(Note 6.1)
NXT ID3
(R/W)
CKP3
TEST
NID3
TID3
ET2
D3
EF
A3
NO-SYNC
SUB-AD2
RECON
TENTID
PLANE
BACK-
CKP2
TID2
NID2
NXT
A10
ID2
D2
A2
RCN-TM1
SUB-AD1
SUB-AD1
NXT ID1
NEXTID
CKP1
NID1
TID1
TMA
NEW
A9
A1
D1
SMSC COM20022I 3V
A0/ SWAP
RCM-TM2
SUB-AD0
SUB-AD0
NXT ID0
SLOW-
Datasheet
NID0
TID0
LSB
ARB
TTA
TA/
D0
A8
X
ADDR
07-0
07-1
07-2
07-3
07-4
00
01
02
03
04
05
06

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