COM20022I3V-HD SMSC, COM20022I3V-HD Datasheet - Page 25

• Manufacturer Part Number: COM20022I3V-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20022I3V-HD

• Data Rate: 10 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
SMSC COM20022I 3V
Sampled A2-A0, nCS
nRD doesn't delay. By this modification, the internal real address and Chip Select are stable while the
internal real read signal is active. Refer to Figure 5.7.
The I/O address and Chip Select signals, which are supplied to the data output logic, are not sampled.
Also, the nRD signal is not delayed, because the above sampling and delaying paths decrease the data
access time of the read cycle.
The above sampling and delaying signals are supplied to the Read Pulse Generation logic which
generates the clearing pulse for the Diagnostic register and generates the starting pulse of the RAM
Arbitration. Typical delay time between nRD and nRD1 is around 15nS and between nRD1 and nRD2 is
around 10nS.
Longer pulse widths are needed due to these delays on nRD signal. However, the CPU can insert some
wait cycles to extend the width without any impact on performance.
The BUSTMG pin is used to support this function. It is used to Enable/Disable the High Speed CPU Read
and Write function. It is defined as: BUSTMG = 0, the High Speed CPU Read and Write operations are
enabled; BUSTMG = 1, the High Speed CPU Read and Write operations are disabled if the RBUSTMG bit
is 0. If BUSTMG = 1 and RBUSTMG = 1, High Speed CPU Read operations are enabled (see definition of
RBUSTMG bit below).
The RBUSTMG bit was added to Disable/Enable the High Speed CPU Read function. It is defined as:
RBUSTMG=0, Disabled (Default); RBUSTMG=1, Enabled.
In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply.
BUSTMG PIN
More delayed nRD
Delayed nRD
(nRD2)
A2-A0, nCS
0
1
1
(nRD1)
nRD
Figure 5.7
RBUSTMG BIT
- High Speed CPU Bus Timing – Intel CPU Mode
X
0
1
DATASHEET
High Speed CPU Read and Write
Normal Speed CPU Read and Write
High Speed CPU Read and Normal Speed CPU Write
Page 25
VALID
VALID
BUS TIMING MODE
Revision 02-27-06