CYIH1SM1000AA-HHCS Cypress Semiconductor Corp, CYIH1SM1000AA-HHCS Datasheet - Page 64

• Manufacturer Part Number: CYIH1SM1000AA-HHCS
• Description: IC SPACE IMAGE SENSOR 84-JLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIH1SM1000AA-HHCS

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The reference voltages can be either injected by a power supply
voltage or can be generated from a resistance divider. See
Input Range Setting”
8.4 Device handling
8.4.1 Handling Precautions
The component is susceptible to damage by electro-static
discharge. Therefore, suitable precautions shall be employed for
protection during all phases of manufacture, testing, packaging,
shipment and any handling.
9. Frequent Asked Questions
Question:
In my datasheet for the HAS2, the pixel readout timing diagram is lacking some information I need. It appears SYNC_X should change
on the rising edge of CLK_X. And while SYNC_X is high, a rising edge of CLK_X should sync XRD to X1 register. But the diagram
shows SYNC_X high for 2 CLK_X periods. Due to timing variations, SYNC_X could technically be high for as many as 3 different
rising edges of CLK_X! The timing diagram doesn't show any setup or hold timing for SYNC_X and CLK_X.
Answer:
CLK_X is divided internally in the sensor. SYNC_X is based upon this divided clock. When SYNC_X is high for a even pair of this
divided clock cycles the XRD will be pushed the length of this even pair of clock cycles. Though, when SYNC_X drops during an
un-even pair of divided clock cycles it is unclear what XRD will do. But this behavior is most unlikely.
Question:
RES_REGn doesn't have any timing info either. It's the asynchronous reset for internal registers. How long must it be held low?
Answer:
To be on the safe side you have to keep it low for at least 1us.
You can apply the following sequence when powering up the sensor:
■
■
■
Question:
The ADC serial interface timing diagram is incomplete. It appears the SPI_DATA is supposed to change on the falling edge of
SPI_CLK.
period of 1000 ns, so the SPI_DATA would be present for 500 ns prior to the rising edge of SPI_CLK. But what is the SPI_DATA setup
time for the *first* rising edge of SPI_CLK (first bit of data)?
Answer:
The best way to operate the device is to change your SPI data during the falling edge of the SPI clock. This gives you plenty of time
before the data is being sampled on the rising edge of the SPI clock.
Document Number: 001-54123 Rev. *A
Power on device with known register settings
During power on, keep RES_REGn low for at least 1us
Apply Line/column address upload timing diagram
If so, then what is the setup and hold times of the SPI_DATA around the rising edge of SPI_CLK? The SPI_CLK has a
on page 60.
“ADC
Until proven otherwise by evaluation testing these devices must
be considered as Class 0 in the HBM ESDS component classifi-
cation. This specification can possibly be widened when the
results of the evaluation test program are known.
8.4.2 Storage Information
The components must be stored in a dust-free and temperature-,
humidity and ESD controlled environment.
The specific storage conditions are mentioned in
9 of this specification.
CYIH1SM1000AA-HHCS
Table 2
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