CYIH1SM1000AA-HHCS Cypress Semiconductor Corp, CYIH1SM1000AA-HHCS Datasheet - Page 55

• Manufacturer Part Number: CYIH1SM1000AA-HHCS
• Description: IC SPACE IMAGE SENSOR 84-JLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIH1SM1000AA-HHCS

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Multiplexer operation:
Changing gain during read out
It's possible to change the gain settings during the read out of 1 line. The following procedure is suggested.
For example: gain changing between pixel 56 and 57
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■
■
■
■
■
■
The total time needed to change the gain settings is about 450 ns
Hard Reset - Soft Reset - Hard-to-Soft Reset
See
The ADC is a pipelined device that samples on each rising edge of its clock CLK_ADC. The output DATA is updated on each falling
edge of CLK_ADC. There is an input-to-output latency of 6.5 clock cycles.
Document Number: 001-54123 Rev. *A
When pixel 56 comes out, stop the x clock after the falling edge.
The output stays at the same level of this pixel (see
Change the gain settings by setting the internal registers as described in section
Assert the CAL signal for 200 ns but leave the BLANK signal inactive
After the CAL signal has felled down, wait 50 ns.
Reactivate the X clock starting with the rising edge
The first pixel that comes out is pixel 57
MODE.PGA[2..0]
t
t
t
t
t
“Reset Modes Timing Controls”
1
2
3
4
5
000
001
010
100
101
011
110
111
input setup
input hold
sample clock
Latency
output delay
Description
Selected input
pixel array
TEMP
on page 61.
AIN3
AIN4
AIN1
AIN2
-
-
100 ns
20 ns
5 ns
Min
Figure 41. ADC Timing Diagram
Figure 38
10 ns
6.5t
Typ
3
on page 53)
Max
50% duty cycle required, +/-5%
exact
8.2.5
on page 56
CYIH1SM1000AA-HHCS
Remarks
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