CYIH1SM1000AA-HHCS Cypress Semiconductor Corp, CYIH1SM1000AA-HHCS Datasheet - Page 45

• Manufacturer Part Number: CYIH1SM1000AA-HHCS
• Description: IC SPACE IMAGE SENSOR 84-JLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYIH1SM1000AA-HHCS

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.1.1 Pixel Architecture
A square array contains 1024x1024 three-transistor linearly-integrating pixels of each 18 x 18
reset line, for power, an output select line, and eventually the pixel's output signal
There are three transistors in a pixel. The first one acts as a
switch between the power supply and the photodiode. The
photodiode is equivalent to a capacitor with a light-controlled
current source. The second transistor is a source follower
amplifier, buffering the voltage at the photodiode/capacitor
cathode for connection to the outside world. The third transistor
again is a switch, connecting the output of the buffer amplifier to
an output signal bus.
Activating the reset line drains the charges present on the pixel's
embedded photodiode capacitor, corresponding to a black, dark,
pre-exposure state, or high voltage. As all pixels on a row (line)
share their reset control lines, the pixels in a row can only be
reset together.
With both reset and select lines disabled the pixel amasses
photo charges on its capacitor, charges generated in the photo-
Document Number: 001-54123 Rev. *A
Figure 27. Three-transistor Pixe: Transistor-level Diagram (left), and Functional Equivalent (right)
Figure 28. Signal Lifetime in a Three-transistor Pixel: Reset to black level (high voltage),
Photo Charge Integration (dropping voltage), voltage readout
diode by impinging photons. During this integration the voltage
on the photodiode cathode decreases.
When the select line is asserted the voltage on the capacitor is
connected to the pixel output through the source follower buffer
transistor.
All pixels in a line have their select lines tied together: upon
selection a whole line of pixel output signals is driven onto the
1024 column buses that lead into the column amplifiers for
further processing and complete or partial sequential readout to
the ADC.
All pixels on a line have their reset lines tied together: the reset
mechanism works on all pixels in a line simultaneously, no
individual or addressed pixel reset (IPR) is possible.
CYIH1SM1000AA-HHCS
μ
m. Each pixel has a connection for a
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