EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 43

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EP4CGX75DF27C7N

Manufacturer Part Number
EP4CGX75DF27C7N
Description
Cyclone IV GX
Manufacturer
Altera
Series
CYCLONE® IV GXr

Specifications of EP4CGX75DF27C7N

Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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0
Chapter 3: Memory Blocks in Cyclone IV Devices
Memory Modes
Memory Modes
Single-Port Mode
© November 2009 Altera Corporation
f
1
1
You can selectively enable asynchronous clears per logical memory using the
Quartus II RAM MegaWizard
For more information, refer to the
There are three ways to reset registers in the M9K blocks:
Cyclone IV devices M9K memory blocks allow you to implement fully-synchronous
SRAM memory in multiple modes of operation. Cyclone IV devices M9K memory
blocks do not support asynchronous (unregistered) memory inputs.
M9K memory blocks support the following modes:
Violating the setup or hold time on the M9K memory block input registers may
corrupt memory contents. This applies to both read and write operations.
Single-port mode supports non-simultaneous read and write operations from a single
address.
devices M9K memory blocks.
Figure 3–6. Single-Port Memory
Notes to
(1) You can implement two single-port memory blocks in a single M9K block.
(2) For more information, refer to
Power up the device
Use the aclr signal for output register only
Assert the device-wide reset signal using the DEV_CLRn option
Single-port
Simple dual-port
True dual-port
Shift-register
ROM
FIFO
Figure
Figure 3–6
3–6:
shows the single-port memory configuration for Cyclone IV
“Packed Mode Support” on page
data[ ]
address[ ]
wren
byteena[]
addressstall
inclocken
rden
aclr
inclock
(Note
Plug-In Manager.
RAM Megafunction User
1),
(2)
3–4.
outclocken
outclock
q[]
Cyclone IV Device Handbook, Volume 1
Guide.
3–7

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