EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 365
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EP4CGX75DF27C7N
Manufacturer Part Number
EP4CGX75DF27C7N
Description
Cyclone IV GX
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX75DF27C7N
Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX75DF27C7N
Manufacturer:
SONGCHUAN
Quantity:
1 000
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Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Top-Level Port Lists
Table 1–29. Multipurpose PLL, General Purpose PLL and Miscellaneous Ports in ALTGX Megafunction for
Cyclone IV GX (Part 2 of 2)
© December 2010 Altera Corporation
Reset &
Power
Down
Reconfigu
ration
Calibration
Block
Test Mode
Block
gxb_powerdown
tx_digitalreset
rx_analogreset
rx_digitalreset
reconfig_clk
reconfig_togxb
reconfig_fromgxb
cal_blk_clk
cal_blk_powerdown
rx_bistdone
rx_bisterr
Port Name
Output
Input
Input
Input
Input
Input
Input
Output
Input
Input
Output
Output
Input/
Asynchronous signal
Asynchronous signal.
The minimum pulse
width is two parallel
clock cycles.
Asynchronous signal.
The minimum pulse
width is two parallel
clock cycles.
Asynchronous signal.
The minimum pulse
width is two parallel
clock cycles.
Clock signal
Asynchronous signal
Asynchronous signal
Clock signal
Asynchronous signal
Asynchronous signal
Asynchronous signal
Clock Domain
Transceiver block power down.
■
■
Transmitter PCS reset.
■
Receiver PMA reset.
■
Receiver PCS reset.
■
Dynamic reconfiguration clock.
■
■
From the dynamic reconfiguration controller.
To the dynamic reconfiguration controller.
Clock for the transceiver calibration block.
Calibration block power down control.
BIST or PRBS test completion indicator.
■
■
BIST or PRBS verifier error indicator
■
■
When asserted, all digital and analog circuitry in the PCS,
HSSI, CDR, and PCIe modules are powered down.
Asserting the gxb_powerdown signal does not power down
the refclk buffers.
When asserted, the transmitter PCS blocks are reset.
When asserted, analog circuitry in the receiver PMA block is
reset.
When asserted, the receiver PCS blocks are reset.
Also used for offset cancellation except in PIPE mode.
For the supported frequency range for this clock, refer to
Cyclone IV Device Data Sheet
A high level during BIST test mode indicates the verifier either
receives complete pattern cycle or detects an error and stays
asserted until being reset using the rx_digitalreset
port.
A high level during PRBS test mode indicates the verifier
receives complete pattern cycle and stays asserted until being
reset using the rx_digitalreset port.
In BIST test mode, the signal stays asserted upon detecting an
error until being reset using the rx_digitalreset port.
In PRBS test mode, the signal asserts for a minimum of 3
rx_clkout clock cycles upon detecting an error and
deasserts if the following PRBS sequence contains no error.
Cyclone IV Device Handbook, Volume 2
Description
chapter.
1–85
the
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