EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 39

• Manufacturer Part Number: EP4CGX75DF27C7N
• Description: Cyclone IV GX
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX75DF27C7N

• Number Of Logic Elements/cells: 73920
• Number Of Labs/clbs: 4620
• Total Ram Bits: 4257792
• Number Of I /o: 310
• Number Of Gates: -
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: *
• Operating Temperature: 0°C ~ 85°C
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 3: Memory Blocks in Cyclone IV Devices
Overview
Control Signals
Parity Bit Support
Byte Enable Support
© November 2009 Altera Corporation
The clock-enable control signal controls the clock entering the input and output
registers and the entire M9K memory block. This signal disables the clock so that the
M9K memory block does not see any clock edges and does not perform any
operations.
The rden and wren control signals control the read and write operations for each
port of M9K memory blocks. You can disable the rden or wren signals independently
to save power whenever the operation is not required.
Parity checking for error detection is possible with the parity bit along with internal
logic resources. Cyclone IV devices M9K memory blocks support a parity bit for each
storage byte. You can use this bit as either a parity bit or as an additional data bit. No
parity function is actually performed on this bit.
Cyclone IV devices M9K memory blocks support byte enables that mask the input
data so that only specific bytes of data are written. The unwritten bytes retain the
previous written value. The wren signals, along with the byte-enable (byteena)
signals, control the write operations of the RAM block. The default value of the
byteena signals is high (enabled), in which case writing is controlled only by the
wren signals. There is no clear port to the byteena registers. M9K blocks support
byte enables when the write port has a data width of ×16, ×18, ×32, or ×36 bits.
Byte enables operate in one-hot manner, with the LSB of the byteena signal
corresponding to the least significant byte of the data bus. For example, if
byteena = 01 and you are using a RAM block in ×18 mode, data[8..0] is
enabled and data[17..9] is disabled. Similarly, if byteena = 11, both
data[8..0] and data[17..9] are enabled. Byte enables are active high.
Table 3–2
Table 3–2. byteena for Cyclone IV Devices M9K Blocks
Note to
(1) Any combination of byte enables is possible.
byteena[3..0]
[0] = 1
[1] = 1
[2] = 1
[3] = 1
Table
lists the byte selection.
3–2:
datain
[15..8]
[7..0]
—
—
× 16
datain
[17..9]
[8..0]
—
—
× 18
Affected Bytes
(Note 1)
datain
[23..16]
[31..24]
[15..8]
[7..0]
Cyclone IV Device Handbook, Volume 1
× 32
datain
[26..18]
[35..27]
[17..9]
[8..0]
× 36
3–3