EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 109
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4CGX75DF27C7N
Manufacturer Part Number
EP4CGX75DF27C7N
Description
Cyclone IV GX
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX75DF27C7N
Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX75DF27C7N
Manufacturer:
SONGCHUAN
Quantity:
1 000
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© December 2010 Altera Corporation
CYIV-51006-2.2
This chapter describes the I/O and high speed I/O capabilities and features offered in
Cyclone
The I/O capabilities of Cyclone IV devices are driven by the diversification of I/O
standards in many low-cost applications, and the significant increase in required I/O
performance. Altera’s objective is to create a device that accommodates your key
board design needs with ease and flexibility.
The I/O flexibility of Cyclone IV devices is increased from the previous generation
low-cost FPGAs by allowing all I/O standards to be selected on all I/O banks.
Improvements to on-chip termination (OCT) support and the addition of true
differential buffers have eliminated the need for external resistors in many
applications, such as display system interfaces.
High-speed differential I/O standards have become popular in high-speed interfaces
because of their significant advantages over single-ended I/O standards. The
Cyclone IV devices support LVDS, BLVDS, RSDS, mini-LVDS, and PPDS. The
transceiver reference clocks and the existing general-purpose I/O (GPIO) clock input
features also support the LVDS I/O standards.
The Quartus
that allow you to plan and optimize I/O system designs even before the design files
are available.
This chapter includes the following sections:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
“Cyclone IV I/O Elements” on page 6–2
“I/O Element Features” on page 6–3
“OCT Support” on page 6–7
“I/O Standards” on page 6–12
“Termination Scheme for I/O Standards” on page 6–13
“I/O Banks” on page 6–16
“Pad Placement and DC Guidelines” on page 6–22
“Clock Pins Functionality” on page 6–23
“High-Speed I/O Interface” on page 6–23
“High-Speed I/O Standards Support” on page 6–27
“True Output Buffer Feature” on page 6–35
“High-Speed I/O Timing” on page 6–36
“Design Guidelines” on page 6–38
“Software Overview” on page 6–39
®
IV devices.
®
II software completes the solution with powerful pin planning features
6. I/O Features in Cyclone IV Devices
Cyclone IV Device Handbook, Volume 1
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