EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 41
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EP4CGX75DF27C7N
Manufacturer Part Number
EP4CGX75DF27C7N
Description
Cyclone IV GX
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX75DF27C7N
Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX75DF27C7N
Manufacturer:
SONGCHUAN
Quantity:
1 000
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Chapter 3: Memory Blocks in Cyclone IV Devices
Overview
© November 2009 Altera Corporation
Figure 3–2. Cyclone IV Devices Address Clock Enable Block Diagram
The address clock enable is typically used to improve the effectiveness of cache
memory applications during a cache-miss. The default value for the address clock
enable signals is low.
Figure 3–3
write cycles, respectively.
Figure 3–3. Cyclone IV Devices Address Clock Enable During Read Cycle Waveform
latched address
(inside memory)
addressstall
q (asynch)
rdaddress
q (synch)
inclock
and
rden
Figure 3–4
doutn-1
doutn
addressstall
an
address[N]
address[0]
a0
clock
doutn
show the address clock enable waveform during read and
a0
dout0
a1
dout0
dout1
a2
address[N]
address[0]
register
register
dout1
a1
dout1
a3
dout1
dout1
Cyclone IV Device Handbook, Volume 1
address[0]
address[N]
a4
dout1
a4
dout4
a5
dout4
a5
dout5
a6
3–5
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