DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 33

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.0
The CPU has a 16-bit (data) modified Harvard architec-
ture with an enhanced instruction set, including signifi-
cant support for digital signal processing. The CPU has
a 24-bit instruction word, with a variable length opcode
field. The Program Counter (PC) is 24 bits wide and
addresses up to 4M x 24 bits of user program memory
space.
An instruction prefetch mechanism helps maintain
throughput and provides predictable execution. Most
instructions execute in a single-cycle effective execu-
tion rate, with the exception of instructions that change
the program flow, the double-word move (MOV.D)
instruction, PSV accesses, and the table instructions.
Overhead free program loop constructs are supported
using the DO and REPEAT instructions, both of which
are interruptible at any point.
3.1
Devices have sixteen 16-bit Working registers in the
programmer’s model. Each of the Working registers
can act as a data, address or address offset register.
The 16th Working register (W15) operates as a soft-
ware Stack Pointer for interrupts and calls. The working
registers, W0 through W3, and selected bits from the
STATUS register, have shadow registers for fast con-
text saves and restores using a single POP.S or
PUSH.S instruction.
3.2
The dsPIC33EPXXXMU806/810/814 instruction set
has two classes of instructions: the MCU class of
instructions and the DSP class of instructions. The
PIC24EPXXXGU810/814 instruction set has the MCU
class of instructions and does not support DSP instruc-
tions. These two instruction classes are seamlessly
integrated into the architecture and execute from a sin-
gle execution unit. The instruction set includes many
addressing modes and was designed for optimum
C compiler efficiency.
 2009-2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
2: Some registers and associated bits
CPU
Registers
Instruction Set
of the dsPIC33EPXXXMU806/810/814
and PIC24EPXXXGU810/814 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70359) in the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
Preliminary
in
3.3
The base data space can be addressed as 32K words
or 64 Kbytes and is split into two blocks, referred to as
X and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operate solely through the X
memory AGU, which accesses the entire memory map
as one linear data space. On dsPIC33EPXXXMU806/
810/814 devices, certain DSP instructions operate
through the X and Y AGUs to support dual operand
reads, which splits the data address space into two
parts. The X and Y data space boundary is device
specific.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary. The program-to-data-
space mapping feature, known as Program Space
Visibility (PSV), lets any instruction access program
space as if it were data space. Moreover, the Base
Data Space address is used in conjunction with a read
or write page register (DSRPAG or DSWPAG) to form
an Extended Data Space (EDS) address. The EDS can
be addressed as 8 Mwords or 16 Mbytes. Refer to
Section 3. “Data Memory” (DS70595) and Section 4.
“Program Memory” (DS70613) in the “dsPIC33E/
PIC24E Family Reference Manual” for more details on
EDS, PSV and table accesses.
On
overhead-free circular buffers (Modulo Addressing) are
supported in both X and Y address spaces. The
Modulo Addressing removes the software boundary-
checking overhead for DSP algorithms. The X AGU
circular addressing can be used with any of the MCU
class of instructions. The X AGU also supports Bit-
Reverse Addressing to greatly simplify input or output
data
PIC24EPXXXGU810/814 devices do not support
Modulo and Bit-Reverse Addressing.
3.4
The CPU supports these addressing modes:
• Inherent (no operand)
• Relative
• Literal
• Memory Direct
• Register Direct
• Register Indirect
Each instruction is associated with a predefined
Addressing mode group, depending upon its functional
requirements. As many as six Addressing modes are
supported for each instruction.
reordering
dsPIC33EPXXXMU806/810/814
Data Space Addressing
Addressing Modes
for
radix-2
FFT
DS70616E-page 33
algorithms.
devices,