DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 279

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 16-11: PWMCONx: PWM CONTROL REGISTER (CONTINUED)
 2009-2011 Microchip Technology Inc.
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
2:
3:
4:
5:
Software must clear the interrupt status here and in the corresponding IFS bit in the interrupt controller.
These bits should not be changed after the PWM is enabled (PTEN = 1).
DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored.
The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
DTC<1:0>: Dead-Time Control bits
11 = Dead-Time Compensation mode
10 = Dead-time function is disabled
01 = Negative dead time actively applied for Complementary Output mode
00 = Positive dead time actively applied for all output modes
DTCP: Dead-Time Compensation Polarity bit
When set to ‘1’:
If DTCMPx = 0, PWMLx is shortened and PWMHx is lengthened.
If DTCMPx = 1, PWMHx is shortened and PWMLx is lengthened.
When set to ‘0’:
If DTCMPx = 0, PWMHx is shortened and PWMLx is lengthened.
If DTCMPx = 1, PWMLx is shortened and PWMHx is lengthened.
Unimplemented: Read as ‘0’
MTBS: Master Time Base Select bit
1 = PWM generator uses the secondary master time base for synchronization and as the clock source
0 = PWM generator uses the primary master time base for synchronization and as the clock source
CAM: Center-Aligned Mode Enable bit
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
XPRES: External PWM Reset Control bit
1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base
0 = External pins do not affect PWM time base
IUE: Immediate Update Enable bit
1 = Updates to the active MDC/PDCx/SDCx registers are immediate
0 = Updates to the active PDCx registers are synchronized to the PWM time base
for the PWM generation logic (if secondary time base is available)
for the PWM generation logic
mode
Preliminary
(2,4)
(5)
(3)
DS70616E-page 279