DSPIC33EP512MU810T-I/PT Microchip Technology, DSPIC33EP512MU810T-I/PT Datasheet - Page 31

• Manufacturer Part Number: DSPIC33EP512MU810T-I/PT
• Description: 100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP512MU810T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 512KB (170K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 24K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.5
The PGECx and PGEDx pins are used for ICSP and
debugging purposes. It is recommended to keep the
trace length between the ICSP connector and the ICSP
pins on the device as short as possible. If the ICSP con-
nector is expected to experience an ESD event, a
series resistor is recommended, with the value in the
range of a few tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(V
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB
ICE™.
For more information on MPLAB ICD 3 and MPLAB
REAL ICE connection requirements, refer to the
following documents that are available on the
Microchip web site.
• “Using MPLAB
• “MPLAB
• “MPLAB
• “Using MPLAB
2.6
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator. For details, see
“Oscillator Configuration”
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in
 2009-2011 Microchip Technology Inc.
IH
Guide” DS51616
(poster) DS51749
) and input low (V
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
®
ICSP Pins
External Oscillator Pins
PICkit™ 3, MPLAB ICD 3, or MPLAB REAL
®
®
ICD 3 Design Advisory” DS51764
REAL ICE™ In-Circuit Emulator User’s
®
®
REAL ICE™” In-Circuit Emulator
ICD 3” (poster) DS51765
IL
) requirements.
for details.
Figure
2-3.
Section 9.0
Preliminary
FIGURE 2-3:
2.7
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 3 MHz < F
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
2.8
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor between V
and unused pins and drive the output to logic low.
Main Oscillator
Guard Ring
Guard Trace
Secondary
Oscillator
Oscillator Value Conditions on
Device Start-up
Unused I/Os
IN
< 5.5 MHz to comply with device PLL
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
DS70616E-page 31
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