CY8C3665PVI-008 Cypress Semiconductor Corp, CY8C3665PVI-008 Datasheet - Page 111

• Manufacturer Part Number: CY8C3665PVI-008
• Description: CY8C3665PVI-008
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665PVI-008

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 67MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: SSOP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.6.4 External Crystal Oscillator
Table 11-80. ECO AC Specifications
11.6.5 External Clock Reference
Table 11-81. External Clock Reference AC Specifications
11.6.6 Phase-Locked Loop
Table 11-82. PLL DC Specifications
Table 11-83. PLL AC Specifications
Document Number: 001-53413 Rev. *K
F
I
Fpllin
Fpllout
Jperiod-rms Jitter (rms)
Notes
Parameter
Parameter
Parameter
DD
Parameter
61. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
62. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
63. Based on device characterization (Not production tested).
Crystal frequency range
External frequency range
Input duty cycle range
Input edge rate
PLL operating current
PLL input frequency
PLL intermediate frequency
PLL output frequency
Lock time at startup
[63]
Description
Description
Description
Description
[61]
[61]
[62]
Measured at V
V
In = 3 MHz, Out = 67 MHz
In = 3 MHz, Out = 24 MHz
Output of prescaler
IL
to V
[63]
IH
Conditions
Conditions
Conditions
Conditions
DDIO
/2
PSoC
Min
Min
Min
Min
4
0.1
30
24
0
–
–
1
1
–
–
®
3: CY8C36 Family
Typ
Typ
Typ
400
200
Typ
–
50
–
–
–
–
–
–
–
Data Sheet
Max
25
Max
Max
Max
250
250
33
70
48
67
Page 111 of 125
–
–
–
3
Units
MHz
Units
Units
Units
MHz
MHz
MHz
MHz
V/ns
µA
µA
µs
ps
%
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