CY8C3665PVI-008 Cypress Semiconductor Corp, CY8C3665PVI-008 Datasheet - Page 106

• Manufacturer Part Number: CY8C3665PVI-008
• Description: CY8C3665PVI-008
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665PVI-008

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 67MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: SSOP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5.3 Interrupt Controller
Table 11-70. Interrupt Controller AC Specifications
11.5.4 JTAG Interface
Table 11-71. JTAG Interface AC Specifications
Document Number: 001-53413 Rev. *K
f_TCK
T_TDI_setup
T_TMS_setup
T_TDI_hold
T_TDO_valid
T_TDO_hold
Notes
55. Based on device characterization (Not production tested).
56. f_TCK must also be no more than 1/3 CPU clock frequency.
Parameter
Parameter
TDI setup before TCK high
TDI, TMS hold after TCK high
TCK low to TDO valid
TDO hold after TCK high
TCK frequency
TMS setup before TCK high
Delay from interrupt signal input to ISR
code execution from ISR code
TDO
TMS
TDI
TCK
Description
Description
T_TMS_setup
T_TDI_setup
Figure 11-66. JTAG Interface Timing
[55]
T_TDI_hold
T_TMS_hold
3.3 V ≤ V
1.71 V ≤ V
T = 1/f_TCK max
T = 1/f_TCK max
T = 1/f_TCK max
Includes worse case completion of
longest instruction DIV with 6
cycles
(1/f_TCK)
DDD
DDD
Conditions
Conditions
≤ 5 V
< 3.3 V
T_TDO_valid
PSoC
(T/10) – 5
T_TDO_hold
Min
Min
T/4
T/4
T/4
–
–
–
®
–
3: CY8C36 Family
Typ
Typ
–
–
–
–
–
–
–
–
Data Sheet
Max
14
2T/5
25
Max
7
Page 106 of 125
[56]
–
–
–
–
[56]
Tcy CPU
Units
Units
MHz
MHz
ns
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