ADSP-21369KSWZ-1A Analog Devices Inc, ADSP-21369KSWZ-1A Datasheet - Page 46

• Manufacturer Part Number: ADSP-21369KSWZ-1A
• Description: 266 MHz, Shared Memory,S/PDIF EPAD PBfr
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KSWZ-1A

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / Rohs Status: Compliant

ADSP-21367/ADSP-21368/ADSP-21369
SPI Interface—Slave
Table 41. SPI Interface Protocol—Slave Switching and Timing Specifications
1
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral
SPICLKS
SPICHS
SPICLS
SDSCO
HDS
SSPIDS
HSPIDS
SDPPW
DSOE
DSOE
DSDHI
DSDHI
DDSPIDS
HDSPIDS
DSOV
Interface Port” chapter.
1
1
CPHASE = 1
CPHASE = 0
(OUTPUT)
(OUTPUT)
(CP = 0)
(CP = 1)
(INPUT)
SPICLK
(INPUT)
SPICLK
(INPUT)
(INPUT)
(INPUT)
SPIDS
MISO
MOSI
MISO
MOSI
t
t
t
SDSCO
DSOE
DSOV
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE = 0)
SPIDS Assertion to Data Out Active
SPIDS Assertion to Data Out Active (SPI2)
SPIDS Deassertion to Data High Impedance
SPIDS Deassertion to Data High Impedance (SPI2)
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
t
t
SPICHS
SSPIDS
t
DDSPIDS
MSB
t
MSB VALID
SPICLS
MSB VALID
MSB
t
DDSPIDS
Rev. E | Page 46 of 60 | July 2009
Figure 36. SPI Slave Timing
t
t
SPICLS
SPICHS
t
SSPIDS
t
DDSPIDS
LSB VALID
t
SPICLKS
LSB
t
HDSPIDS
t
SSPIDS
LSB VALID
t
HSPIDS
Min
4 × t
2 × t
2 × t
2 × t
2 × t
2
2
2 × t
0
0
0
0
2 × t
t
HSPIDS
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
t
HDS
LSB
– 2
– 2
– 2
t
SDPPW
t
t
t
Max
6.8
8
6.8
8.6
9.5
5 × t
DSDHI
HDSPIDS
DSDHI
PCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns