ADSP-21369KSWZ-1A Analog Devices Inc, ADSP-21369KSWZ-1A Datasheet - Page 26

• Manufacturer Part Number: ADSP-21369KSWZ-1A
• Description: 266 MHz, Shared Memory,S/PDIF EPAD PBfr
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KSWZ-1A

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / Rohs Status: Compliant

ADSP-21367/ADSP-21368/ADSP-21369
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
Table 20. Precision Clock Generator (Direct Pin Routing)
1
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
D = FSxDIV, and PH = FSxPHASE. For more information, see the processor hardware reference, “Precision Clock Generators” chapter.
In normal mode.
PCGIP
STRIG
HTRIG
DPCGIO
DTRIGCLK
DTRIGFS
PCGOW
1
Input Clock Period
PCG Trigger Setup Before Falling
Edge of PCG Input Clock
PCG Trigger Hold After Falling
Edge of PCG Input Clock
PCG Output Clock and Frame Sync Active Edge
Delay After PCG Input Clock
PCG Output Clock Delay After PCG Trigger
PCG Frame Sync Delay After PCG Trigger
Output Clock Period
PCK_CLKx_O
PCG_TRIGx_I
PCG_EXTx_I
PCG_FSx_O
DAI_Pm
DPI_Pm
(CLKIN)
DAI_Pn
DPI_Pn
DAI_Py
DPI_Py
DAI_Pz
DPI_Pz
t
STRIG
Figure 15. Precision Clock Generator (Direct Pin Routing)
t
DPCGIO
t
t
DTRIGCLK
Rev. E | Page 26 of 60 | July 2009
HTRIG
t
DTRIGFS
Min
t
4.5
3
2.5
2.5 + (2.5 × t
2.5 + ((2.5 + D – PH) × t
2 × t
PCLK
t
× 4
DPCGIO
PCGIP
t
PCGIW
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01–20).
– 1
PCGIP
)
PCGIP
)
t
PCGOW
Max
10
10 + (2.5 × t
10 + ((2.5 + D – PH) × t
PCGIP
)
PCGIP
)
Unit
ns
ns
ns
ns
ns
ns
ns