ADSP-21369KSWZ-1A Analog Devices Inc, ADSP-21369KSWZ-1A Datasheet - Page 45

• Manufacturer Part Number: ADSP-21369KSWZ-1A
• Description: 266 MHz, Shared Memory,S/PDIF EPAD PBfr
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KSWZ-1A

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / Rohs Status: Compliant

SPI Interface—Master
The processors contain two SPI ports. The primary has dedi-
cated pins and the secondary is available through the DPI. The
timing provided in
to both.
Table 40. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
HDSPIDM
SDSCIM
HDSM
SPITDM
CPHASE = 1
CPHASE = 0
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
FLAG3–0
(CP = 0)
(CP = 1)
SPICLK
SPICLK
(INPUT)
(INPUT)
MOSI
MISO
MOSI
MISO
Table 40
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge
Last SPICLK Edge to FLAG3–0IN High
Sequential Transfer Delay
t
SSPIDM
t
and
SDSCIM
MSB VALID
Table 41 on Page 46
t
HSPIDM
t
t
SPICHM
SPICLM
MSB
VALID
MSB
t
SSPIDM
t
t
MSB
SPICLM
SPICHM
t
DDSPIDM
Rev. E | Page 45 of 60 | July 2009
t
HSPIDM
applies
t
Figure 35. SPI Master Timing
DDSPIDM
ADSP-21367/ADSP-21368/ADSP-21369
t
HDSPIDM
LSB VALID
t
SPICLKM
LSB
LSB VALID
t
HDSPIDM
Min
8.2
2
8 × t
4 × t
4 × t
4 × t
4 × t
4 × t
4 × t
t
SSPIDM
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
t
HDSM
– 2
– 2
– 2
– 2
– 2
– 2
– 1
t
HSPIDM
LSB
t
SPITDM
Max
2.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns