ADSP-21369KSWZ-1A Analog Devices Inc, ADSP-21369KSWZ-1A Datasheet - Page 36

• Manufacturer Part Number: ADSP-21369KSWZ-1A
• Description: 266 MHz, Shared Memory,S/PDIF EPAD PBfr
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KSWZ-1A

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / Rohs Status: Compliant

ADSP-21367/ADSP-21368/ADSP-21369
1
This figure reflects changes made to support left-justified sample pair mode.
(DATA CHANNEL
(DATA CHANNEL
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SCLK)
(SCLK)
A/B)
A/B)
(FS)
(FS)
NOTES
1. SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20–1 PINS.
THE CHARACTERIZED SPORT AC TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND
FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH THE SRU.
DRIVE
DRIVE
t
t
DDTLFSE
DDTLFSE
t
t
DDTENFS
DDTENFS
t
t
SFSE/I
SFSE/I
Figure 23. External Late Frame Sync
Rev. E | Page 36 of 60 | July 2009
SAMPLE
SAMPLE
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
t
t
HFSE/I
HFSE/I
1ST BIT
1ST BIT
LATE EXTERNAL TRANSMIT FS
DRIVE
DRIVE
t
t
HDTE/I
HDTE/I
1
t
t
DDTE/I
DDTE/I
2ND BIT
2ND BIT