ADSP-21369KSWZ-1A Analog Devices Inc, ADSP-21369KSWZ-1A Datasheet - Page 40

• Manufacturer Part Number: ADSP-21369KSWZ-1A
• Description: 266 MHz, Shared Memory,S/PDIF EPAD PBfr
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KSWZ-1A

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / Rohs Status: Compliant

ADSP-21367/ADSP-21368/ADSP-21369
Pulse-Width Modulation Generators
Table 34. PWM Timing
Sample Rate Converter—Serial Input Port
The SRC input signals SCLK, frame sync (FS), and SDATA are
routed from the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided in
DAI_P20–1 pins.
Table 35. SRC, Serial Input Port
1
Parameter
Switching Characteristics
t
t
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
PWMW
PWMP
SRCSFS
SRCHFS
SRCSD
SRCHD
SRCCLKW
SRCCLK
1
1
1
1
OUTPUTS
PWM
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
PWM Output Pulse Width
PWM Output Period
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SDATA)
(SCLK)
(FS)
Table 35
are valid at the
t
Figure 28. SRC Serial Input Port Timing
PWMW
Rev. E | Page 40 of 60 | July 2009
t
Figure 27. PWM Timing
SRCCLKW
t
SRCSD
t
SRCSFS
SAMPLE EDGE
t
PWMP
Min
t
2 × t
PCLK
– 2
PCLK
– 1.5
t
t
SRCHFS
SRCHD
t
SRCCLK
Min
4
5.5
4
5.5
(t
t
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Max
(2
(2
16
16
– 2) × t
– 1) × t
Max
PCLK
PCLK
– 2
– 1.5
Unit
ns
ns
Unit
ns
ns
ns
ns
ns
ns