AD9779A-EBZ Analog Devices Inc, AD9779A-EBZ Datasheet - Page 43

• Manufacturer Part Number: AD9779A-EBZ
• Description: Dual 16B, 1.0 GSPS TxDAC
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9779A-EBZ

• Design Resources: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
• Number Of Dac's: 2
• Number Of Bits: 16
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9779A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DATACLKDIV only affects the DATACLK output frequency
and not the frequency of the data sampling clock. To maintain
an f
consistent with the expected data rate, DATACLKDIV should
be set to 00.
Table 24. DACCLK to DATACLK Divisor Values
Variable
IF
ZS
SP
DATACLKDIV
INPUT DATA REFERENCED TO REFCLK
In some systems, it may be more convenient to use the REFCLK
input rather than the DATACLK output as the input data timing
reference. If the frequency of DACCLK is equal to the frequency
of the data input (no interpolation is used), then the Data with
Respect to REFCLK± timing specifications of Table 25 apply
directly without further considerations. If the frequency of
DACCLK is greater than the frequency of the input data, a
divider is used to generate the DATACLK output (and the
internal data sampling clock). This divider creates a phase
ambiguity between REFCLK and DATACLK, which results in
uncertainty in the sampling time. In order to establish fixed
setup and hold times of the data interface, this phase ambiguity
must be eliminated.
To eliminate the phase ambiguity, the SYNC_I input pins (Pin 13
and Pin 14) must be used to force the data to be sampled on a
specific REFCLK edge. The relationship between REFCLK,
SYNC_I, and the input data is shown in Figure 84 and Figure 85.
Therefore, both SYNC_I and DATA must meet the timing in
Table 25 for reliable data transfer into the device.
Table 25. Data Timing Specifications vs. Temperature
Timing Parameter
Data with Respect to REFCLK±
Data with Respect to DATACLK
SYNC_I± to REFCLK±
DATACLK
frequency that samples the input data that remains
Value
Interpolation factor
1, if zero stuffing is disabled
2, if zero stuffing is enabled
0.5, if single port is enabled
1, if dual port is selected
1, 2, or 4
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
−40°C
+25°C
+85°C
−40°C to +85°C
−40°C
+25°C
+85°C
−40°C to +85°C
0x01
0x01
0x02
0x03
Register
Address
Min t
−0.80
−1.00
−1.10
−0.80
2.50
2.70
3.00
0.30
0.25
0.15
0.30
3.00
S
(ns)
Bit
<7:6>
<0>
<6>
<5:4>
Rev. A | Page 43 of 60
Min t
3.50
3.80
3.80
−0.05
−0.20
−0.40
0.75
0.90
0.90
3.35
−0.05
0.65
PLL Disabled
H
(ns)
Note that even though the setup and hold time of SYNC_I
is relative to REFCLK, the SYNC_I input is sampled at the
internal DACCLK rate. In the case where the PLL is employed,
SYNC_I must be asserted to meet the setup time with respect to
REFCLK (t
rising edge of the internal SYNC_I sample clock. In other words,
the SYNC_I assert edge has to be placed between its successive
keep out windows that replicate at the DACCLK rate and not
the REFCLK rate. The valid window for asserting SYNC_I is
shaded gray in Figure 85 for the case where the PLL provides a
DACCLK frequency of four times the REFCLK frequency.
Thus, the minimum setup time is t
setup time is t
DACCLK
More details of the synchronization circuitry are found in the
Device Synchronization section of this data sheet.
Figure 84. Input Data Port Timing, Data Referenced to REFCLK, f
REFCLK
REFCLK
SYNC_I
SYNC_I
DATA
DATA
Min KOW (ns)
2.55
2.50
2.70
3.00
2.45
2.50
2.60
2.95
0.95
1.00
1.05
1.20
Figure 85. Input Data Port Timing, Data Referenced to REFCLK,
S_SYNC
DACCLK
), but cannot be asserted prior to the previous
t
SREFCLK
AD9776A/AD9778A/AD9779A
t
− t
DACCLK
Min t
−0.83
−1.06
−1.19
−0.83
2.50
2.70
3.00
3.00
0.27
0.19
0.06
0.27
H_SYNC
f
DACCLK
t
SREFCLK
t
HREFCLK
S
.
t
(ns)
S_SYNC
= f
t
H_SYNC
REFCLK
S_SYNC
Min t
3.87
4.04
4.37
4.37
−0.05
−0.20
−0.40
−0.05
1.17
1.29
1.47
1.47
× 4
PLL Enabled
t
HREFCLK
t
S_SYNC
and the maximum
t
H_SYNC
H
(ns)
Min KOW (ns)
2.99
2.98
3.16
3.54
2.45
2.50
2.60
2.95
1.39
1.48
1.51
1.74
DACCLK
= f
REFCLK