AD9779A-EBZ Analog Devices Inc, AD9779A-EBZ Datasheet - Page 30

• Manufacturer Part Number: AD9779A-EBZ
• Description: Dual 16B, 1.0 GSPS TxDAC
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9779A-EBZ

• Design Resources: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
• Number Of Dac's: 2
• Number Of Bits: 16
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9779A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9776A/AD9778A/AD9779A
Register Name
AUX DAC2 Control
Interrupt
Version
Register
Address
0x12
0x11
0x12
0x12
0x12
0x19
0x19
0x19
0x19
0x19
0x19
0x1F
Bits
1:0
7:0
7
6
5
7
6
4
3
2
0
7:0
Parameter
Auxiliary DAC2 Data<9:8>
Auxiliary DAC2 Data<7:0>
Auxiliary DAC2 Sign
Auxiliary DAC2 Current
Direction
Auxiliary DAC2 Power-Down
Data Timing Error IRQ
Sync Timing Error IRQ
Data Timing Error Type
Data Timing Error IRQ Enable
Sync Timing Error IRQ Enable
Internal Sync Loopback
Version<7:0>
Rev. A | Page 30 of 60
Function
AUX DAC2 10-bit output current control word.
Magnitude of the AUX DAC current increases with
increasing value. Bit 9 is the MSB and Bit 0 is the LSB.
1: AUX2_N active
0: source
1: sink
1: AUX DAC2 off
Read only. Active high indicates a timing violation
occurred on the input data port. The IRQ is latched.
This bit is cleared when the Interrupt register is
read.
Read only. Active high indicates a timing violation
occurred on the SYNC_I input. The IRQ is latched.
This bit is cleared when the Interrupt register is
read.
Read only. Indicates the timing error type.
0: hold time violation
1: setup time violation
Meaningful when Data Timing Error IRQ is active.
1: Data Timing Error IRQ is enabled
0: Sync Timing Error IRQ is masked
1: Sync Timing Error IRQ is enabled
The received SYNC_I signal is looped back to the
SYNC_O output pins.
0: AUX2_P active
0: AUX DAC2 on
0: Data Timing Error IRQ is masked
Indicates device hardware revision number.
Default
00
00000000
0
0
0
0
0
0
0
0
00000011