AD9254-150EBZ Analog Devices Inc, AD9254-150EBZ Datasheet - Page 14

• Manufacturer Part Number: AD9254-150EBZ
• Description: 1.8V 14Bit 150 MSPS ADC EB
• Manufacturer: Analog Devices Inc

Specifications of AD9254-150EBZ

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 150M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 506mW @ 150MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9254
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9254
THEORY OF OPERATION
The AD9254 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. The pipeline
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding samples.
Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage consists only of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9254 is a differential switched
capacitor SHA that has been designed for optimum
performance while processing a differential input signal.
The clock signal alternately switches the SHA between sample
mode and hold mode (see Figure 31). When the SHA is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within one-half of a clock
cycle. A small resistor in series with each input can help reduce
the peak transient current required from the output stage of the
driving source.
A shunt capacitor can be placed across the inputs to provide
dynamic charging currents. This passive network creates a low-
pass filter at the ADC input; therefore, the precise values are
dependent upon the application.
In IF undersampling applications, any shunt capacitors should
be reduced. In combination with the driving source impedance,
these capacitors would limit the input bandwidth. For more
information, see Application Note AN-742, Frequency Domain
Response of Switched-Capacitor ADCs; Application Note AN-827,
A Resonant Approach to Interfacing Amplifiers to Switched-
Capacitor ADCs; and the Analog Dialogue article,
Coupled Front-End for Wideband A/D Converters. ”
“Transformer-
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For best dynamic performance, the source impedances driving
VIN+ and VIN− should match such that common-mode settling
errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates two reference
voltages used to define the input span of the ADC core. The
span of the ADC core is set by the buffer to be 2 × VREF. The
reference voltages are not available to the user. Two bypass points,
REFT and REFB, are brought out for decoupling to reduce the
noise contributed by the internal reference buffer. It is recom-
mended that REFT be decoupled to REFB by a 0.1 μF capacitor,
as described in the Layout Considerations section.
Input Common Mode
The analog inputs of the AD9254 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device such that V
recommended for optimum performance; however, the device
functions over a wider range with reasonable performance (see
Figure 30). An on-board common-mode voltage reference is
included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD). The CML pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Layout
Considerations section.
VIN+
VIN–
C
C
PIN, PAR
PIN, PAR
Figure 31. Switched-Capacitor SHA Input
S
S
H
C
C
S
S
CM
= 0.55 × AVDD is
C
C
S
S
H
H