AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 50

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7193
Figure 65 shows the filter response when FS[9:0] is set to 5 and
the post filter averages by 16. In this case, the output data rate is
equal to 53.33 Hz when the first filter notch is placed at 60 Hz.
The rejection at 60 Hz ± 0.5 Hz is equal to 40 dB minimum.
Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is
set to 30 and the postfilter averages by 16. The output data rate
is equal to 8.9 Hz whereas the rejection at 50 Hz ± 0.5 Hz and
60 Hz ± 0.5 Hz is typically 42 dB.
–100
–110
–120
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
Figure 65. Filter Response for Average + Decimate Filter
Figure 66. Filter Response for Average + Decimate Filter
0
0
(Sinc
(Sinc
30
30
3
3
Filter, FS[9:0] = 30, Average by 16)
Filter, FS[9:0] = 5, Average by 16)
FREQUENCY (Hz)
FREQUENCY (Hz)
60
60
90
90
120
120
150
15
0
Rev. B | Page 50 of 56
Simultaneous 50 Hz and 60 Hz rejection is also achieved by using
an FS word of 96 and averaging by 16, which places a notch at
50 Hz. Setting the REJ60 bit to 1 places a notch at 60 Hz (see
Figure 67). The output data rate is reduced to 2.78 Hz with this
configuration, but the rejection is improved to 94 dB typically at
50 Hz ± 1 Hz and 60 Hz ± 1 Hz.
FAST SETTLING MODE (CHOP ENABLED)
Chop can be enabled in the fast settling mode. With chop
enabled, the ADC offset and offset drift are minimized. The
analog input pins are continuously swapped. With the analog
input pins connected in one direction, the settling time of the
sinc filter is allowed and a conversion is recorded. The analog
input pins are then inverted, and another settled conversion is
obtained. Subsequent conversions are averaged so that the offset
is minimized. This continuous swapping of the analog input
pins and the averaging of subsequent conversions means that
the offset drift is also minimized.
Chopping does not change the output data rate. However, the
settling time equals
Consequently, if chop is enabled, the sinc
is set to 6, averaging by 16 is enabled, and the output data rate is
equal to 42.1 Hz. Therefore, the conversion time equals 1/42.10 Hz
or 23.75 ms, and the settling time is equal to 47.5 ms.
t
SETTLE
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
Figure 67. Filter Response for Average + Decimate Filter
0
= 2/f
(Sinc
ADC
3
30
Filter, FS[9:0] = 96, Average by 16)
FREQUENCY (Hz)
60
90
4
filter is selected, FS[9:0]
120
150