AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 43

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Sinc
Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
is allowed for each conversion. Therefore, the conversion time
when converting on a single channel or when converting on
several channels is constant. The user does not need to consider
the effects of channel changes on the output data rate. When the
channel sequencer is enabled, the AD7193 automatically operates
in zero latency mode.
The output data rate equals
where:
f
f
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
When the analog input is constant or a channel change occurs,
valid conversions are available at a constant output data rate.
When conversions are being performed on a single channel and
a step change occurs on the analog input, the ADC continues to
output fully settled conversions if the step change is synchronized
with the conversion process. If the step change is asynchronous,
one conversion is output from the ADC that is not completely
settled (see Figure 39).
Table 31 provides examples of output data rates and the
corresponding FS values.
Table 31. Examples of Output Data Rates and the
Corresponding Settling Time (Zero Latency)
FS[9:0]
480
96
80
ADC
CLK
is the master clock (4.92 MHz nominal).
is the output data rate.
3
f
ANALOG
OUTPUT
ADC
Zero Latency
INPUT
ADC
= 1/ t
SETTLE
Figure 39. Sinc
Output Data Rate (Hz)
3.3
16.7
20
= f
CLK
/(3 × 1024 × FS[9:0])
3
Zero Latency Operation
1/
f
ADC
Settling Time (ms)
300
60
50
SETTLED
FULLY
Rev. B | Page 43 of 56
Sinc
Figure 40 show the frequency response of the sinc
FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The
output data rate is equal to 50 Hz when zero latency is disabled
and 16.7 Hz when zero latency is enabled. The sinc
50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock.
When FS[9:0] is set to 80 and the master clock equals 4.92 MHz,
60 Hz rejection is achieved (see Figure 41). The output data rate
is equal to 60 Hz when zero latency is disabled and 20 Hz when
zero latency is enabled. The sinc
minimum at 60 Hz ± 1 Hz, assuming a stable master clock.
3
–100
–120
–110
–100
–120
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
50 Hz/60 Hz Rejection
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
0
Figure 40. Sinc
Figure 41. Sinc
25
30
50
3
3
FREQUENCY (Hz)
FREQUENCY (Hz)
Filter Response (FS[9:0] = 96)
Filter Response (FS[9:0] = 80)
60
75
3
filter has rejection of 95 dB
90
100
120
125
3
3
filter when
AD7193
filter gives
150
150