AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 48

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7193
50 Hz/60 Hz Rejection, Sinc
Figure 57 shows the frequency response when FS[9:0] is set to 6
and the postfilter averages by 16. This gives an output data rate
of 42.10 Hz when the master clock equals 4.92 MHz. The sinc
filter places the first notch at
The postfiltering places notches at f
averaging) and multiples of this frequency; therefore, when FS[9:0]
is set to 6 and the postfilter averaging is 16, a notch is placed at
800 Hz due to the sinc filter and notches are placed at 50 Hz
and multiples of 50 Hz due to the postfilter. The notch at 50 Hz
is a first-order notch; therefore, the notch is not wide. This means
that the rejection at 50 Hz exactly is good, assuming a stable
4.92 MHz master clock. However, in a band of 50 Hz ± 1 Hz, the
rejection degrades significantly. The rejection at 50 Hz ± 0.5 Hz is
40 dB minimum, assuming a stable clock; therefore, a good master
clock source is recommended when using fast settling mode.
Figure 58 shows the filter response when FS[9:0] is set to 5 and
the postfilter averages by 16. In this case, the output data rate is
equal to 50.53 Hz (4.92 MHz master clock) while the first filter
notch is placed at 60 Hz. The rejection at 60 Hz ± 0.5 Hz is equal to
40 dB minimum.
f
NOTCH
–100
–110
–120
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
Figure 57. Filter Response for Average + Decimate Filter
Figure 58. Filter Response for Average + Decimate Filter
0
0
= f
CLK
(Sinc
(Sinc
/(1024 × FS[9:0])
30
30
4
4
Filter, FS[9:0] = 6, Average by 16)
Filter, FS[9:0] = 5, Average by 16)
FREQUENCY (Hz)
FREQUENCY (Hz)
60
60
4
Filter
NOTCH
90
90
/Avg (Avg is the amount of
120
120
15
150
0
Rev. B | Page 48 of 56
Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is
set to 30 and the postfilter averages by 16. The output data rate
is equal to 8.4 Hz, whereas the rejection at 50 Hz ± 0.5 Hz and
60 Hz ± 0.5 Hz is typically 44 dB.
Simultaneous 50 Hz and 60 Hz rejection is also achieved by
using an FS word of 96 and averaging by 16; this places a notch
at 50 Hz. Setting the REJ60 bit to 1 places a notch at 60 Hz (see
Figure 60). The output data rate is reduced to 2.63 Hz with this
configuration but the rejection is improved to typically 100 dB
at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz.
–100
–120
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
Figure 59. Filter Response for Average + Decimate Filter
0
Figure 60. Filter Response for Average + Decimate Filter
0
0
(Sinc
(Sinc
30
4
4
30
Filter, FS[9:0] = 30, Average by 16)
Filter, FS[9:0] = 96, Average by 16)
FREQUENCY (Hz)
60
FREQUENCY (Hz)
60
90
90
120
120
150
150