AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 46

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7193
CHOP ENABLED (SINC
With chop enabled, the ADC offset and offset drift are minimized.
The analog input pins are continuously swapped. With the analog
input pins connected in one direction, the settling time of the
sinc filter is allowed and a conversion is recorded. The analog
input pins invert and another settled conversion is obtained.
Subsequent conversions are averaged to minimize the offset.
This continuous swapping of the analog input pins and the
averaging of subsequent conversions means that the offset drift
is also minimized. With chop enabled, the resolution increases
by 0.5 bits. Using the sinc
for output data rates up to 320 Hz.
Output Data Rate and Settling Time (Sinc
For the sinc
where:
f
f
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The value of FS[9:0] can be varied from 1 to 1023. This results
in an output data rate of 1.56 Hz to 1600 Hz. The settling time is
equal to
Table 33. Examples of Output Data Rates and the
Corresponding Settling Time (Chop Enabled, Sinc
FS[9:0]
96
80
When a channel change occurs, the modulator and filter are reset.
The complete settling time is required to generate the first
conversion after the channel change. Subsequent conversions
on this channel occur at 1/f
ADC
CLK
CONVERSIONS
is the master clock (4.92 MHz nominal).
is the output data rate.
f
t
ADC
SETTLE
CHANNEL
= f
CHOP
= 2/f
3
CLK
Figure 50. Channel Change (Sinc
Figure 49. Chop Enabled (Sinc
filter, the output data rate is equal to
/(3 × 1024 × FS[9:0])
CH A
ADC
Output Data Rate (Hz)
16.7
20
CHANNEL A
MODULATOR
CH A CH A
3
filter with chop enabled is suitable
ADC
3
FILTER)
.
ADC
SINC
3
/SINC
1/
3
CH B
Chop Enabled)
f
CHANNEL B
4
ADC
3
Chop Enable)
CH B
POST FILTER
Settling Time (ms)
120
100
3
Chop Enabled)
CH B
CH B
3
Filter)
CH B
Rev. B | Page 46 of 56
If conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in analog
input; therefore, it continues to output conversions at the
programmed output data rate. However, it is at least two
conversions later before the output data accurately reflects
the analog input. If the step change occurs while the ADC is
processing a conversion, then the ADC takes three conversions
after the step change to generate a fully settled result.
The cutoff frequency f
50 Hz/60 Hz Rejection (Sinc
When FS[9:0] is set to 96 and chopping is enabled, the filter
response shown in Figure 52 is obtained. The output data rate
is equal to 16.7 Hz for a 4.92 MHz master clock. The chopping
introduces notches at odd integer multiples of f
due to the sinc filter in addition to the notches introduced by
the chopping means that simultaneous 50 Hz and 60 Hz rejection
is achieved for an output data rate of 16.7 Hz. The rejection at
50 Hz/60 Hz ± 1 Hz is typically 53 dB, assuming a stable
master clock.
Figure 51. Asynchronous Step Change in Analog Input (Sinc
f
–100
–110
–120
3dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
Figure 52. Sinc
ANALOG
OUTPUT
0
= 0.24 × f
0
INPUT
ADC
25
ADC
3
Filter Response (FS[9:0] = 96, Chop Enabled)
3dB
1/
f
50
ADC
is equal to
FREQUENCY (Hz)
3
Chop Enabled)
75
100
SETTLED
FULLY
ADC
/2. The notches
125
3
Chop Enabled)
150