AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 25
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
AD7193BCPZ
Manufacturer Part Number
AD7193BCPZ
Description
4ch VeryLow Noise 24Bit SD ADC With PGA
Manufacturer
Analog Devices Inc
Datasheet
1.AD7193BRUZ-REEL.pdf
(56 pages)
Specifications of AD7193BCPZ
Number Of Bits
24
Sampling Rate (per Second)
4.8k
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
32-WFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MD2
1
1
1
1
MD1
0
0
1
1
MD0
0
1
0
1
Mode
Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the
calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a
calibration. The measured offset coefficient is placed in the offset register of the selected channel.
Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration.
RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed
in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the
selected channel. A full-scale calibration is recommended each time that the gain of a channel is changed to
minimize the full-scale error. When AV
internal full-scale calibration.
System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as
selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is recommended
each time that the gain of a channel is changed.
System full-scale calibration. The user should connect the system full-scale input to the channel input pins as
selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and
returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is recommended
each time the gain of a channel is changed.
Rev. B | Page 25 of 56
DD
is less than 4.75 V, the CLK_DIV bit must be set when performing the
AD7193