AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 28

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7193
DATA REGISTER
RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000
The conversion result from the ADC is stored in this data register.
This is a read-only, 24-bit register. Upon completion of a read
operation from this register, the RDY pin/bit is set. When the
DAT_STA bit in the mode register is set to 1, the contents of the
status register are appended to each 24-bit conversion. This is
advisable when several analog input channels are enabled because
the four LSBs of the status register (CHD3 to CHD0) identify
the channel from which the conversion originated.
ID REGISTER
RS2, RS1, RS0 = 100; Power-On/Reset = 0xX2
The identification number for the AD7193 is stored in the ID
register. This is a read-only register.
GP7
0(0)
Table 25. GPOCON Register (GP) Bit Designations
Bit Location
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
GP6
BPDSW(0)
Bit Name
0
BPDSW
GP32EN
GP10EN
P3DAT
P2DAT
P1DAT
P0DAT
GP5
GP32EN(0)
Description
This bit must be programmed with a Logic 0 for proper operation.
Bridge power-down switch control bit.
This bit is set by the user to close the bridge power-down switch BPDSW to AGND. The switch can sink up
to 30 mA.
The bit is cleared by the user to open the bridge power-down switch. When the ADC is placed in power-
down mode, the bridge power-down switch remains active.
Digital Output P3 and Digital Output P2 enable.
When GP32EN is set, the P3 and P2 digital outputs are active.
When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored.
Digital Output P1 and Digital Output P0 enable.
When GP10EN is set, the P1 and P0 digital outputs are active. The P1 and P0 pins can be used as a reference
input to REFIN2 when the REFSEL bit in the configuration register is set to 1.
When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are ignored.
Digital Output P3.
When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin. When P3DAT is
high, the P3 output pin is high.
When P3DAT is low, the P3 output pin is low. When the GPOCON register is read, the P3DAT bit reflects the
status of the P3 pin if GP32EN is set.
Digital Output P2.
When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin. When P2DAT is
high, the P2 output pin is high.
When P2DAT is low, the P2 output pin is low. When the GPOCON register is read, the P2DAT bit reflects the
status of the P2 pin if GP32EN is set.
Digital Output P1.
When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin. When P1DAT is
high, the P1 output pin is high.
When P1DAT is low, the P1 output pin is low. When the GPOCON register is read, the P1DAT bit reflects the
status of the P1 pin if GP10EN is set.
Digital Output P0.
When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin. When P0DAT is
high, the P0 output pin is high.
When P0DAT is low, the P0 output pin is low. When the GPOCON register is read, the P0DAT bit reflects the
status of the P0 pin if GP10EN is set.
GP4
GP10EN(0)
Rev. B | Page 28 of 56
GP3
P3DAT(0)
GPOCON REGISTER
RS2, RS1, RS0 = 101; Power-On/Reset = 0x00
The GPOCON register is an 8-bit register from which data can
be read or to which data can be written. This register is used to
enable the general-purpose digital outputs.
Table 25 outlines the bit designations for the GPOCON register.
GP0 through GP7 indicate the bit locations. GP denotes that the
bits are in the GPOCON register. GP7 denotes the first bit of
the data stream. The number in parentheses indicates the
power-on/reset default status of that bit.
GP2
P2DAT(0)
GP1
P1DAT(0)
GP0
P0DAT(0)