AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 27

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit Location
CON4
CON3
CON2 to CON0
Table 23. Channel Selection (Pseudo Bit = 0)
Short
1
Table 24. Channel Selection (Pseudo Bit = 1)
Short
1
TEMP
1
TEMP
1
Channel Enable Bits in the Configuration Register
Channel Enable Bits in the Configuration Register
CH7
1
CH7
1
Bit Name
BUF
U/B
G2 to G0
CH6
1
CH6
1
CH5
1
CH5
1
Description
Enables the buffer on the analog inputs.
If BUF is set, the analog inputs are buffered, allowing the user to place source impedances on the front
end without contributing gain errors to the system. When the buffer is enabled, it requires some head-
room; therefore, the voltage on any input pin must be limited to 250 mV within the power supply rails.
If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. With the
buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AV
Polarity select bit.
When this bit is set, unipolar operation is selected.
When this bit is cleared, bipolar operation is selected.
Gain select bits. These bits are written by the user to select the ADC input range as follows:
G2
0
0
0
0
1
1
1
1
CH4
1
CH4
1
G1
0
0
1
1
0
0
1
1
CH3
1
CH3
1
CH2
1
CH2
1
G0
0
1
0
1
0
1
0
1
Rev. B | Page 27 of 56
CH1
1
CH1
1
1
Gain
Reserved
Reserved
8
16
32
64
128
CH0
1
CH0
1
Positive
Input AIN(+)
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AINCOM
Positive
Input AIN(+)
AIN1
AIN3
AIN5
AIN7
AIN1
AIN3
AIN5
AIN7
AIN2
Temperature sensor
Temperature sensor
Channel Enabled
Channel Enabled
ADC Input Range (5 V Reference)
±2.5 V
±312.5 mV
±156.2 mV
±78.125 mV
±39.06 mV
±19.53 mV
Negative
Input AIN(−)
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
AINCOM
Negative
Input AIN(−)
AIN2
AIN4
AIN6
AIN8
AIN2
AIN4
AIN6
AIN8
AIN2
Status
Register
Bits CHD[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Status
Register
Bits CHD[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Calibration
Register Pair
0
1
2
3
4
4
4
4
0
Calibration
Register
Pair
0
1
2
3
0
1
2
3
0
AD7193
DD
.