5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 7

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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MV51002-1.0
Functional Description
MAX V Device Handbook
December 2010
This chapter describes the architecture of the MAX
following sections:
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MAX V devices contain a two-dimensional row- and column-based architecture to
implement custom logic. Row and column interconnects provide signal interconnects
between the logic array blocks (LABs).
Each LAB in the logic array contains 10 logic elements (LEs). An LE is a small unit of
logic that provides efficient implementation of user logic functions. LABs are grouped
into rows and columns across the device. The MultiTrack interconnect provides fast
granular timing delays between LABs. The fast routing between LEs provides
minimum timing delay for added levels of logic versus globally routed interconnect
structures.
The I/O elements (IOEs) located after the LAB rows and columns around the
periphery of the MAX V device feeds the I/O pins. Each IOE contains a bidirectional
I/O buffer with several advanced features. I/O pins support Schmitt trigger inputs
and various single-ended standards, such as 33-MHz, 32-bit PCI™, and LVTTL.
MAX V devices provide a global clock network. The global clock network consists of
four global clock lines that drive throughout the entire device, providing clocks for all
resources within the device. You can also use the global clock lines for control signals
such as clear, preset, or output enable.
“Functional Description” on page 2–1
“Logic Array Blocks” on page 2–4
“Logic Elements” on page 2–8
“MultiTrack Interconnect” on page 2–14
“Global Signals” on page 2–19
“User Flash Memory Block” on page 2–21
“Internal Oscillator” on page 2–22
“Core Voltage” on page 2–25
“I/O Structure” on page 2–26
2. MAX V Architecture
®
V device and contains the
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