5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 11

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 2: MAX V Architecture
Logic Array Blocks
Figure 2–3. LAB Structure for MAX V Devices
Note to
(1) Only from LABs adjacent to IOEs.
December 2010 Altera Corporation
Fast I/O connection
to IOE (1)
DirectLink
interconnect from
adjacent LAB
or IOE
DirectLink
interconnect to
adjacent LAB
or IOE
Figure
2–3:
adjacent LE for fast sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE’s register to the adjacent LE’s register
within an LAB. The Quartus
adjacent LABs, allowing the use of local, LUT chain, and register chain connections
for performance and area efficiency.
Logic Element
LE0
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LAB
®
II software places associated logic within an LAB or
Figure 2–3
Local Interconnect
Row Interconnect
shows the MAX V LAB.
MAX V Device Handbook
Column Interconnect
Fast I/O connection
to IOE (1)
DirectLink
interconnect from
adjacent LAB
or IOE
DirectLink
interconnect to
adjacent LAB
or IOE
2–5