5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 24

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2–18
Table 2–2. Routing Scheme for MAX V Devices
MAX V Device Handbook
LUT Chain
Register Chain
Local
Interconnect
DirectLink
Interconnect
R4 Interconnect
C4 Interconnect
LE
UFM Block
Column IOE
Row IOE
Note to
(1) These categories are interconnects.
Source
Table
2–2:
Chain
LUT
v
—
—
—
—
—
—
—
—
—
The UFM block communicates with the logic array similar to LAB-to-LAB interfaces.
The UFM block connects to row and column interconnects and has local interconnect
regions driven by row and column interconnects. This block also has DirectLink
interconnects for fast connections to and from a neighboring LAB. For more
information about the UFM interface to the logic array, refer too
Block” on page
Table 2–2
Register
Chain
v
—
—
—
—
—
—
—
—
—
lists the MAX V device routing scheme.
Local
2–21.
—
—
—
v
v
v
v
v
—
—
(1)
DirectLink
v
v
v
—
—
—
—
—
—
—
(1)
R4
—
—
—
—
v
v
v
v
—
v
(1)
Destination
C4
v
v
v
v
v
v
—
—
—
—
(1)
v
v
v
—
—
—
—
—
—
—
LE
Block
December 2010 Altera Corporation
UFM
v
—
—
—
—
—
—
—
—
—
Chapter 2: MAX V Architecture
“User Flash Memory
Column
MultiTrack Interconnect
IOE
v
v
—
—
—
—
—
—
—
—
Row
IOE
—
—
v
—
—
—
v
—
—
—
Fast I/O
—
—
—
—
—
—
v
—
—
—
(1)