5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 61

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Figure 3–5. UFM Erase Waveform
Table 3–25. Routing Delay Internal Timing Microparameters for MAX V Devices
May 2011 Altera Corporation
t
t
t
C4
R4
LOCAL
Routing
External Timing Parameters
f
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in
For more information about each external timing parameters symbol, refer to
AN629: Understanding Timing in Altera
OSC_ENA
Program
DRDout
DRShft
ARShft
DRDin
ARDin
DRClk
ARClk
Erase
Busy
Min
—
—
—
5M40Z/ 5M80Z/ 5M160Z/
C4
t
t
5M240Z/ 5M570Z
ADS
1,143
ASU
Max
860
655
t
ACLK
Table 3–32 on page 3–23
Min
—
—
—
9 Address Bits
C5, I5
1,973
1,479
2,947
Max
CPLDs.
t
ADH
t
AH
t
EB
t
OSCS
Min
—
—
—
t
through
EPMX
C4
t
OSCH
5M1270Z/ 5M2210Z
Max
561
445
731
Table 3–36 on page
t
BE
Min
—
—
—
C5, I5
MAX V Device Handbook
Max
690
548
899
3–25.
Unit
ps
ps
ps
3–19