5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 10

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2–4
Figure 2–2. Device Floorplan for MAX V Devices
Note to
(1) The device shown is a 5M570Z device. 5M1270Z and 5M2210Z devices have a similar floorplan with more LABs. For 5M40Z, 5M80Z, 5M160Z,
Logic Array Blocks
MAX V Device Handbook
and 5M240Z devices, the CFM and UFM blocks are located on the left side of the device.
Figure
Logic Array
I/O Blocks
I/O Blocks
I/O Blocks
2 GCLK
2–2:
Inputs
Blocks
Figure 2–2
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect,
a look-up table (LUT) chain, and register chain connection lines. There are 26 possible
unique inputs into an LAB, with an additional 10 local feedback input lines fed by LE
outputs in the same LAB. The local interconnect transfers signals between LEs in the
same LAB. LUT chain connections transfer the LUT output from one LE to the
shows a floorplan of a MAX V device.
(Note 1)
CFM Block
UFM Block
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
2 GCLK
Inputs
Logic Array
Blocks
Logic Array Blocks