LFE2-50E-H-EV Lattice, LFE2-50E-H-EV Datasheet - Page 99

• Manufacturer Part Number: LFE2-50E-H-EV
• Description: MCU, MPU & DSP Development Tools LatticeECP2 Eval Brd - Advanced
• Manufacturer: Lattice

Specifications of LFE2-50E-H-EV

• Processor To Be Evaluated: LatticeECP2 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeECP2/M sysCONFIG Port Timing Specifications (Continued)
Lattice Semiconductor
Figure 3-14. sysCONFIG Parallel Port Read Cycle
t
t
1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of the PROGRAMN.
2. For SED (Soft Error Detect), the SEDCLKIN operating frequency must be at least 20MHz. SEDCLKIN is derived from Master Clock Fre-
Master Clock Frequency
Duty Cycle
SUSPI
HSPI
quency that has a +/-30% variation..
Parameter
Parameter
WRITEN
SOSPI Data Setup Time Before CCLK
SOSPI Data Hold Time After CCLK
CCLK
CS1N
BUSY
D[0:7]
*n = last byte of read cycle.
CSN
Selected value - 30%
Over Recommended Operating Conditions
Min.
40
t
t
Description
SUCS
SUWD
Byte 0
t
BSCL
3-47
Byte 1
t
CORD
Selected value + 30%
Max.
t
60
DCB
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
t
Byte 2
BSCYC
t
BSCH
Byte n*
Min.
t
t
7
2
HCS
HWD
Units
MHz
Max.
%
—
—
Units
ns
ns