LFE2-50E-H-EV Lattice, LFE2-50E-H-EV Datasheet - Page 106

• Manufacturer Part Number: LFE2-50E-H-EV
• Description: MCU, MPU & DSP Development Tools LatticeECP2 Eval Brd - Advanced
• Manufacturer: Lattice

Specifications of LFE2-50E-H-EV

• Processor To Be Evaluated: LatticeECP2 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Descriptions (Cont.)
Lattice Semiconductor
[LOC]_SQ_VCCIBm
[LOC]_SQ_VCCOBm
[LOC]_SQ_HDOUTNm
[LOC]_SQ_HDOUTPm
[LOC]_SQ_HDINNm
[LOC]_SQ_HDINPm
[LOC]_SQ_VCCTXm
[LOC]_SQ_VCCRXm
1. These signals are relevant for LatticeECP2M family.
2. m defines the associated channel in the Quad.
3. These signals are defined in Quads [LOC] indicates the corner SERDES Quad is located: ULC (upper left), URC (upper right), LLC (lower
4. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage,
5. There may be SPLLs that do not have dedicated I/Os.
left), LRC (lower right).
care must be given. For more information, refer to TN1159,
Signal Name
4
4
I/O
—
—
—
—
O
O
I
I
Input buffer power supply, channel m (1.2V/1.5V). This pin should be left float-
ing if the channel is unused.
Output buffer power supply, channel m (1.2V/1.5V). This pin should be left
floating if the channel is unused.
High-speed output, negative channel m
High-speed output, positive channel m
High-speed input, negative channel m
High-speed input, positive channel m
Transmitter power supply, channel m (1.2V). This pin must be tied to 1.2V
even if the channel is unused.
Receiver power supply, channel m (1.2V). This pin must be tied to 1.2V even if
the channel is unused.
LatticeECP2/M Pin Assignment
4-3
LatticeECP2/M Family Data Sheet
Description
Recommendations.
Pinout Information