LFE2-50E-H-EV Lattice, LFE2-50E-H-EV Datasheet - Page 243
LFE2-50E-H-EV
Manufacturer Part Number
LFE2-50E-H-EV
Description
MCU, MPU & DSP Development Tools LatticeECP2 Eval Brd - Advanced
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2-50E-H-EV
Processor To Be Evaluated
LatticeECP2 FPGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
Number
Ball
M15
R12
D10
D11
D12
D13
D14
T16
E11
F10
M2
H8
H9
P9
R5
T1
D4
D5
D6
D7
E6
E8
E9
F7
F8
F9
J3
J8
J9
Function
Ball/Pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LFE2M20E/SE
Bank
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Dual Function
Differential
4-140
Function
Ball/Pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LatticeECP2/M Family Data Sheet
Bank
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LFE2M35E/SE
Function
Dual
Pinout Information
Differential
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