LFE2-50E-H-EV Lattice, LFE2-50E-H-EV Datasheet - Page 15

no-image

LFE2-50E-H-EV

Manufacturer Part Number
LFE2-50E-H-EV
Description
MCU, MPU & DSP Development Tools LatticeECP2 Eval Brd - Advanced
Manufacturer
Lattice
Datasheet

Specifications of LFE2-50E-H-EV

Processor To Be Evaluated
LatticeECP2 FPGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
Figure 2-10. Primary Clock Sources for ECP2-50
DLL Input
PLL Input
PLL Input
Clock
Clock
Input
Input
Note: This diagram shows sources for the ECP2-50 device. Smaller LatticeECP2 devices have fewer SPLLs. All LatticeECP2M device
have six SPLLs.
GPLL
SPLL
DLL
CLK
DIV
From Routing
to Eight Quadrant Clock Selection
Clock Input
Primary Clock Sources
Clock Input
Clock Input
2-12
From Routing
Clock Input
LatticeECP2/M Family Data Sheet
GPLL
SPLL
CLK
DLL
DIV
Architecture
PLL Input
Clock
Input
Clock
Input
DLL Input
PLL Input

Related parts for LFE2-50E-H-EV