LFE2-50E-H-EV Lattice, LFE2-50E-H-EV Datasheet - Page 101

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LFE2-50E-H-EV

Manufacturer Part Number
LFE2-50E-H-EV
Description
MCU, MPU & DSP Development Tools LatticeECP2 Eval Brd - Advanced
Manufacturer
Lattice
Datasheet

Specifications of LFE2-50E-H-EV

Processor To Be Evaluated
LatticeECP2 FPGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
Figure 3-18. Configuration from PROGRAMN Timing
Figure 3-19. Wake-Up Timing
Figure 3-20. SPI/SPIm Configuration Waveforms
PROGRAMN
CSSPI[0:1]N
SISPI/BUSY
D7/SPID0
DONE
CCLK
INITN
VCC
DPPDONE
t
PROGRAMN
PROGRAMN
DPPINIT
USER I/O
USER I/O
t
CFG[2:0]
1. The CFG pins are normally static (hard wired)
PRGM
t
ICFG
DONE
DONE
INITN
CCLK
INITN
CCLK
t
DINIT
t
Capture
DPPINIT
t
t
CFGx
DINITD
CFGX
t
CSSPI
Wake-Up
t
CSCCLK
OPCODE
Capture
t
SOE
t
CSPID
t
IOENSS
t
IODISS
D7
0
t
SOCDO
1
D6
t
PRGM
2
D5 D4 D3 D2 D1 D0
3-49
3
4
5
t
MWC
6
t
DINIT
7
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Clock 127
t
XXX
SUCFG
0
Clock 128
Valid
Valid Bitstream
t
HCFG

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