MA160014 Microchip Technology, MA160014 Datasheet - Page 118

• Manufacturer Part Number: MA160014
• Description: MOD PLUG-IN 44PIN PIC18LF45K22
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of MA160014

• Accessory Type: Plug-In Module (PIM) - PIC18LF45K10
• Product: Microcontroller Modules
• Data Bus Width: 8 bit
• Core Processor: PIC18LF45K22
• Interface Type: I2C, SPI
• Operating Supply Voltage: 1.8 V to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PICDEM PIC18 Explorer, DM183032
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
9.5
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are five Peripheral Interrupt
Request Flag registers (PIR1, PIR2, PIR3, PIR4 and
PIR5).
REGISTER 9-4:
DS41412D-page 118
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
PIR Registers
Unimplemented: Read as ‘0’.
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared by software)
0 = The A/D conversion is not complete or has not been started
RC1IF: EUSART1 Receive Interrupt Flag bit
1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART1 receive buffer is empty
TX1IF: EUSART1 Transmit Interrupt Flag bit
1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSART1 transmit buffer is full
SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared by software)
0 = Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared by software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared by software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared by software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared by software)
0 = TMR1 register did not overflow
R/W-0
ADIF
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
W = Writable bit
‘1’ = Bit is set
RC1IF
R-0
TX1IF
R-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSP1IF
R/W-0
Note 1: Interrupt flag bits are set when an
2: User software should ensure the appro-
interrupt condition occurs, regardless of
the state of its corresponding enable bit or
the Global Interrupt Enable bit, GIE/GIEH
of the INTCON register.
priate interrupt flag bits are cleared prior
to enabling an interrupt and after servic-
ing that interrupt.
CCP1IF
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
TMR2IF
R/W-0
TMR1IF
R/W-0
bit 0