CDB42L55 Cirrus Logic Inc, CDB42L55 Datasheet - Page 66

• Manufacturer Part Number: CDB42L55
• Description: Eval Bd Ultra Low Power Stereo Codec
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L55

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L55
• Primary Attributes: 2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: GUI, USB, RS232, I2C Interfaces, USB or External or Battery Power Supply
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1506; CDB-42L55

66
6.33.3 Limiter Soft Ramp Disable
6.34
6.34.1 HPDETECT Pin Status (Read Only)
6.34.2 Serial Port Clock Error (Read Only)
6.34.3 DSP Engine Overflow (Read Only)
6.34.4 MIXx Overflow (Read Only)
HPDETECT
7
Status (Address 29h) (Read Only)
For bits [6:0] in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets these bits to 0.
Configures an override of the digital soft ramp setting.
Indicates the status of the HPDETECT pin.
Indicates the status of the MCLK to LRCK ratio.
Note:
nizes.
Indicates the over-range status in the DSP data path.
Indicates the over-range status in the PCM mix data path.
LIMSRDIS
0
1
HPDETECT
0
1
SPCLKERR
0
1
Application:
DSPxOVFL
0
1
MIXxOVFL
0
1
SPCLKERR
On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
6
Limiter Soft Ramp Disable
OFF; Limiter Attack Rate is dictated by the DIGSFT
ON; Limiter volume changes take effect in one step, regardless of the DIGSFT setting.
Pin State
Low
High
Serial Port Clock Status:
MCLK/LRCK ratio is valid.
MCLK/LRCK ratio is not valid.
“Serial Port Clocking” on page 34
DSP Overflow Status:
No digital clipping has occurred in the data path after the DSP.
Digital clipping has occurred in the data path after the DSP.
PCM Overflow Status:
No digital clipping has occurred in the data path of the ADC and PCM mix of the DSP.
Digital clipping has occurred in the data path of the ADC and PCM mix of the DSP.
DSPBOVFL
5
DSPAOVFL
4
MIXBOVFL
3
(“Digital Soft Ramp” on page
MIXAOVFL
2
ADCBOVFL
46) setting
1
CS42L55
ADCAOVFL
DS773F1
0