CDB42L55 Cirrus Logic Inc, CDB42L55 Datasheet - Page 23

• Manufacturer Part Number: CDB42L55
• Description: Eval Bd Ultra Low Power Stereo Codec
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42L55

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42L55
• Primary Attributes: 2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: GUI, USB, RS232, I2C Interfaces, USB or External or Battery Power Supply
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1506; CDB-42L55

DS773F1
4.2
Analog Inputs
Referenced Control
Analog Front End
PGAxMUX
PDN_ADCx
PGAxVOL[5:0]
PGAB=A
ANLGZCx
ADCxMUX[1:0]
INV_ADCx
PDN_CHRG
HPFRZx
HPFx
HPFx_CF[1:0]
Digital Volume
BOOSTx
ADCxMUTE
ADCxATT[7:0]
DIGSFT
ADCB=A
ALCx
ALCxSRDIS
ALCxZCDIS
ALCARATE[5:0]
ALCRRATE[5:0]
MAX[2:0]
MIN[2:0]
NGALL
NG
THRESH[3:0]
NGDELAY[1:0]
Miscellaneous
DIGSUM[1:0]
DIGMUX
DIGMUX
DIGSUM[1:0]
Swap/
Mix
Register Location
“PGA x Input Select” on page 49
“Power Down ADC x” on page 42
“PGAx Volume” on page 49
“PGA Channel B=A” on page 48
“Analog Zero Cross” on page 46
“ADC x Input Select” on page 46
“Invert ADC Signal Polarity” on page 48
“Power Down ADC Charge Pump” on page 42
“ADCx High-Pass Filter Freeze” on page 47
“ADCx High-Pass Filter” on page 47
“HPF x Corner Frequency” on page 47
“Boostx” on page 49
“ADC Mute” on page 48
“ADCx Volume” on page 50
“Digital Soft Ramp” on page 46
“ADC Channel B=A” on page 48
“ALCx” on page 62
“ALCx Soft Ramp Disable” on page 65
“ALCx Zero Cross Disable” on page 65
“ALC Attack Rate” on page 63
“ALC Release Rate” on page 63
“ALC Maximum Threshold” on page 64
“ALC Minimum Threshold” on page 64
“Noise Gate All Channels” on page 64
“Noise Gate Enable” on page 65
“Noise Gate Threshold and Boost” on page 65
“Noise Gate Delay Timing” on page 65
“Digital Sum” on page 48
“Digital MUX” on page 45
ALCARATE[5:0]
ALCRRATE[5:0]
Figure 9. Analog Input Signal Flow
MAX[2:0]
MIN[2:0]
ALCA
ALCASRDIS
ALCAZCDIS
ALCB
ALCBSRDIS
ALCBZCDIS
ALC
TO DSP Engine
FROM DSP ENGINE
BOOSTA
ADCAMUTE
DIGSFT
ADCAATT[7:0]
ADCB=A
BOOSTB
ADCBMUTE
DIGSFT
ADCBATT[7:0]
ADCB=A
Gain Adjust
Gain Adjust
HPFRZA
HPFA
HPFA_CF[1:0]
Noise Gate
`
HPFRZB
HPB
HPFB_CF[1:0]
NGALL
NG
THRESH[3:0]
NGDELAY[1:0]
PDN_ADCA
INV_ADCA
PDN_CHRG
PDN_ADCB
INV_ADCB
PDN_CHRG
ADCBMUX[1:0]
ADC
ADCAMUX[1:0]
ADC
PDN_ADCA
PGAAVOL[5:0]
PGAB=A
ANLGZC
PDN_ADCB
PGABVOL[5:0]
PGAB=A
ANLGZC
ANALOG PASSTHRU TO
HEADPHONE, LINE AMPLIFIER MUX
PGABMUX
PGAAMUX
CS42L55
AIN2B
AIN1B
AIN1REF
AIN1A
AIN2A
AIN2REF
23