IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 41
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Specifications
Figure 3–2. Architecture of the Transaction Layer: Dedicated Receive Buffer per Virtual Channel
Altera Corporation
December 2006
Towards Application Layer
Virtual Channel 1
Virtual Channel 0
Virtual Channel 0
Virtual Channel 1
Rx0 Data
Rx0 Descriptor
Rx1 Data
Rx1 Descriptor
Tx1 Data
Tx1 Descriptor
Tx1 Control
Tx0 Descriptor
Tx0 Control
Rx0 Control
& Status
Rx1 Control
& Status
Tx0 Data
Interface Established per Virtual Channel
Rx0 Sequencing
Rx1 Sequencing
Tx1 Request
Tx0 Request
Sequencing
Sequencing
& Reordering
& Reordering
Type 0 Configuration Space
Posted & Completion
Posted & Completion
PCI Express Compiler Version 6.1
Receive Buffer
Receive Buffer
Non-Posted
Non-Posted
Check & Reordering
Flow Control Update
Check & Reordering
Flow Control Update
Transaction Layer
Transaction Layer
Flow Control
Flow Control
Packet FIFO
Packet FIFO
Interface Established per Component
Virtual Channel
Arbitration & Tx
Sequencing
Towards Data Link Layer
PCI Express Compiler User Guide
Tx Transaction Layer
Packet Description
& Data
Rx Transaction
Layer Packet
Rx Flow
Control Credits
Tx Flow
Control Credits
Transmit
Data Path
Configuration
Space
Receive
Data Path
3–3
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